This mode is applicable to VFP9-S, VFP10 rev1,VFP11 and VFPv3-based coprocessors.

Hardware floating-point calculations are considerably faster than software calculations. However, VFP coprocessors still require support code for handling of exceptional cases (such as subnormal numbers). In many applications the additional accuracy and IEEE 754 standard compliance provided by the support code are unimportant. In these applications execution speed can be increased and program size reduced by configuring the VFP in RunFast mode.

RunFast mode is not configured by setting a single register bit. It is the combination of the following conditions:

In RunFast mode the VFP coprocessor:

In order to activate RunFast mode, all that is required is to set bits 24 and 25 of the FPSCR, clear the exception bits and activate the VFP. If the code is compiled using "‑‑fpmode std" or "‑‑fpmode fast" bits 24 and 25 of the FPSCR are automatically set and the exceptions cleared by the C runtime library. The RunFast_Enable function is included for completeness should you wish to enable RunFast mode when using a different ‑‑fpmode option.

        AREA RunFast, CODE, READONLY

VFPEnable       EQU     0x40000000
RF_Enable       EQU     2_11:SHL:24
        ; Bit pattern to enable RunFast mode
        ; FPSCR [24] - Flush to Zero mode
        ; FPSCR [25] - Default NaN mode

        EXPORT  RunFast_Enable

RunFast_Enable FUNCTION

        MOV     r0,#RF_Enable
        FMXR    FPSCR, r0       ; FPSCR = r0
        BX      LR
        ENDFUNC


EXPORT  Enable_VFP

Enable_VFP FUNCTION

        ; Enable VFP itself
        MOV     r0,#VFPEnable
        FMXR    FPEXC, r0       ; FPEXC = r0
        BX      LR
        ENDFUNC

        END

As with normal VFP support when using V6 or later coprocessors, RunFast mode requires extra code for Architecture V6 or later (such as coprocessor VFP11) because of the changes to the coprocessor interface. Coprocessors cp10 and cp11 must be enabled by setting bits 20-23 (b1111 gives full read/write access) of the Coprocessor Access Control Register. For more information please refer to the technical reference manual of the ARM11 processor that you are using. The example code below shows how this may be done.

Enable_VFP FUNCTION

if "6" <={ARCHITECTURE}
        MRC p15, 0, r1, c1, c0, 2 ; r1 = Access Control Register
        ORR r1, r1, #(0xf << 20)    ; enable full access for p10,11
        MCR p15, 0, r1, c1, c0, 2 ; Access Control Register = r1
        MOV r1, #0
        MCR p15, 0, r1, c7, c5, 4 ; flush prefetch buffer because of FMXR below
                                  ; and CP 10 & 11 were only just enabled
endif	

        ; Enable VFP itself
        MOV     r0,#VFPEnable
        FMXR    FPEXC, r0       ; FPEXC = r0
        BX      LR
        ENDFUNC