The ARM example code referenced in Section 4.2 was used to produce examples of the number of cycles required to enter and exit Dormant and Shutdown Modes with various memory system configurations. Example cycle times are given in Table 4 through Table 7 for both the ARM1136 and ARM1176 processors, both of which had the following hardware configuration:

Static and dynamic branch prediction were enabled. All TCMs were enabled (as local RAM on ARM1136, not as SmartCache). The memory system configurations used were:

The example code referenced in Dormant and Shutdown Mode Example Code was used without modification to produce example cycle counts. Entry to Dormant or Shutdown Mode was requested by a regularly recurring IRQ interrupt, with a delay of 0x8000 clock cycles between exiting Dormant or Shutdown Mode and the following entry request. The IRQs interrupted the validation test T2-32 from the armv4 suite, which tests shift operations of data processing instructions.

Example cycle counts were produced for both Dormant and Shutdown Mode in all of these memory system configurations, except for saving state to the data TCM, as this is only useful for Dormant Mode. To illustrate the effects of the caches as data and instructions are cached and so the cache hit rate improves, Dormant Mode cycle times are given for both the first time Dormant Mode is entered and exited, with no cache hits, and for the third time Dormant Mode is entered and exited, with most memory accesses hitting in the caches. This effect is not seen in Shutdown Mode as the contents of the caches are lost when the RAMs are powered down. Shutdown Mode cycle times are given both for when the TCMs are assumed to be in use, so their contents are written to main memory and restored using ARM’s internal DMA engine, and for when the TCMs are assumed not to be in use so their contents are not preserved.