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The Power Management Controller (PMC) performs the powering up and powering down of the power domains of the processor. The communication mechanism between the ARM11 processor core and the PMC is not specified by ARM, but could typically be a memory-mapped interface, accessed by the processor performing Strongly-Ordered memory accesses to it.
The precise operation or configuration of the PMC is not specified by ARM due to its application-specific nature. The basic functions related to Dormant and Shutdown Modes that the PMC must provide are:
Determine, for instance when instructed by the processor, that the processor should be put into Dormant or Shutdown Mode.
Wait for the STANDBYWFI output to be asserted by the ARM11 core.
Assert and hold the core Reset pin for at least three clock cycles of CLKIN.
If entering Dormant Mode, while holding Reset, enable the input clamps to all RAMs that will remain powered up during Dormant Mode.
While holding Reset, remove power from the ARM11 processor core, and also from the RAMs if entering Shutdown Mode.
It is the responsibility of the PMC to determine when the core should exit Dormant or Shutdown Mode. This may typically be required when an external interrupt request is detected. When exiting Dormant or Shutdown Mode, the PMC must do the following, in order:
Assert and hold the Reset pin to the ARM11 processor core.
While holding Reset, restore power to the processor.
If exiting Dormant Mode, while holding Reset, disable the input clamps to all RAMs that were active during Dormant Mode.
Release the Reset pin to the processor core.
The PMC must also have the capability to inform the processor what type of reset has occurred. For example, whether the reset was due to exiting Dormant Mode or Shutdown Mode. This notification enables the processor to branch to the correct state restore routine, supplied by the operating system, to correctly restore the state of the processor prior to entry into the low power mode. This also requires the operating system to query the PMC regarding the cause of the reset.
| Copyright © 2006, 2007. All rights reserved. | ARM DAI 0143C |
| Non-Confidential | |
| PDF version All files | |
| Home > Design Considerations for Power Management > Communication with Power Management Controller |