Example AHB design for a Logic Tile on top of the Emulation Baseboards

Application Note 146



Release information

The following changes have been made to this Application Note.

Change history

Date

Issue

Change

October 12, 2005

A

First release

January 18, 2006

B

Getting started section added

June 28, 2006

C

Added support for LT-XC4VLX100+ Virtex 4 logic tiles

May 11, 2007

D

Added HDR net names to Figure 4, support for LT-XC5VLX330 Virtex 5 logic tiles

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The ARM logo, AMBA, Angel, ARMulator, EmbeddedICE, ModelGen, Multi-ICE, ARM7TDMI, ARM9TDMI, TDMI and STRONG are trademarks of ARM Limited.

All other products, or services, mentioned herein may be trademarks of their respective owners.

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1                   Introduction

1.1             Purpose of this application note

 

This application note explains the implementation of AHB and shows how to implement AHB masters and slaves in LT-XC2V4000+, LT-XC4VLX100+, and LT-XC5VLX330 Logic Tiles, so that they can be connected to the Emulation Baseboard HDRX and HDRY buses.

The application note also includes working example Verilog, pre-built FPGA configuration images, and test software for the peripherals in the Logic Tile.

The Integrator and Versatile families of ARM development boards enable customers to implement AMBA AHB masters and slaves.

AMBA AHB is a specification intended for use as an internal bus, in which all masters and slaves are inside an ASIC or FPGA. In AHB the outputs from all the masters are multiplexed, so that only the master that has been granted the bus can access it. Similarly, the outputs from all the slaves are multiplexed, so that only the slave that is being accessed puts its response on the bus.

This revision of the application note includes information and example HDL for the following configurations:

·         An AHB based system, with an Emulation Baseboard and a Logic Tile.

 

Image

Figure 1-1 Core Tile, Logic Tile and EB system

 

 


2                   Getting Started

Before you can use this application note, you will need to program the Emulation Baseboard with the appropriate FPGA image to enable the Core Tile fitted to tile site 1 to function correctly. Please refer to the relevant application note for details on how to do this (for example, AN148). Once you have done this, please follow these steps to program the Logic Tile with the image provided with this application note.

 

1.       Plug the Logic Tile on to TILE SITE 2 of the Emulation Baseboard.

2.       Slide the CONFIG switch (S1) to the ON position.

3.       Connect a RVI or Multi-ICE to the Emulation Baseboard JTAG ICE connector (J18), or a USB cable to the USB Debug Port (J16).

4.       Check that the external supply voltage is +12V (positive on center pin, +/-10%, 35W), and connect it to the power connector (J28).

5.       Power-up the boards. The '3V3 OK' and ‘5V OK’ LEDs on the Emulation Baseboard should both be lit.

6.       If using Multi-ICE, start the Multi-ICE Server, then press ctrl-L and load the relevant manual configuration file from the \boardfiles\multi-ice directory. Depending on the version of Multi-ICE used it may also be necessary to add new devices to Multi-ICE. (Please refer to \boardfiles\irlength_arm.txt for information on how to do this). Please note that Multi-ICE does not support programming of the LT-XC4VLX100+ and LT-XC5VLX330  logic tiles.

7.       If using the USB connection, ensure that your PC has correctly recognised that an ARM® RealView™ ICE Micro Edition device is connected to the USB port. If the Windows operating system requires a USB driver to be installed, please refer to the PB926EJS or EB ...\boardfiles\USB_Debug_driver\readme.txt file.

8.       If using Real View ICE (RVI), you must ensure that the RVI unit is powered and has completed its start-up sequence (check that the LEDs on the front panel have stopped flashing).

9.       You can now run the relevant ‘progcards’ utility for the connection you have prepared above.

 

 

10.   Select the FPGA image you wish to program into the Logic Tile.  The progcards utility will report its progress as the image is programmed into the tile and verified (this may take several minutes a large image).  A successful download will be terminated with the message “Programming Successful”.

11.   Power down the boards.

12.   Set the Logic Tile configuration switches to load flash image 0 to the FPGA (S2 on the logic tile all OFF).

13.   Slide the CONFIG switch on the Emulation Baseboard to the OFF position, and power up the boards.  Check that the 'FPGA_OK’ and GLOBAL_DONE (Emulation Baseboard D35) LEDs are both lit.  The Character LCD should show the Firmware and Hardware versions, indicating that the Boot monitor firmware is running.

14.   The system will now be configured and ready for use.

 

3                   Implementation

3.1             AHB implementation in ARM development boards

 

Figure 3-1 shows a typical implementation of an AHB system inside an ASIC. This AHB system consists of three masters and three slaves.

The left block diagram shows how the outputs of the masters are multiplexed. The output of the multiplexer is routed to the inputs of the slaves. The multiplexer is controlled by the system arbiter, so only one master accesses the bus at one time.

The right block diagram shows how the outputs of the slaves are multiplexed. The output of the multiplexer is routed to the inputs of the masters. The multiplexer is controlled by the system address decoder, so only one slave is accessed at one time. 

 

Image

Figure 3-1: AHB masters and slaves in an ASIC

 

 


 

3.2             Accessing the AHB system bus

 

Since AHB is a pipelined bus, the arbitration, address and data phases of each transfer happen in different cycles.

Figure 3-2 shows the arbitration, address and data phases in an AHB transfer.

 

 

Image

Figure 3-2: Phases in an AHB transfer with no wait states

 


Figure 3-3 shows how to connect the signals from the system bus to the AHB masters in a Logic Tile.

The master inputs HRESP and HREADY are connected directly from the system bus. HRDATA is connected directly to HDATA in the system bus. HDATA contains the data read from a slave during a read cycle.

The master outputs, HADDR and other control signals, are always driven by the AHB baseboard.

HDATA is driven by HWDATA with a tri-state buffer. This buffer is enabled during the data phase of this cycle if the current access is a write access.

 

Image

Figure 3-3: Connections of AHB masters

 


Figure 3-4 shows how to connect the signals from the tri-state system bus to the AHB slaves in a Logic Tile.

The address and control signals, which are slave inputs, are connected directly from the system bus.

HREADYIn is connected directly to HREADY from the system bus. HREADYIn indicates if the last transfer in the system bus has finished, so it is needed by all the AHB slaves.

HWDATA is connected directly to HDATA in the system bus. HDATA contains the data written by a master into a slave during a write cycle.

The slave outputs HRESP and HREADY are multiplexed and drive the signals of the system bus with tri-state buffers. These buffers are enabled if one of the slaves in the Logic Tile is accessed during the address phase of this cycle.

HDATA is driven by HRDATA with a tri-state buffer. This buffer is enabled when one of the slaves in the Logic Tile is accessed during the data phase of this cycle, and if the current access is a read access.

 

 

Image

Figure 3-4: Connection of AHB slaves

 

 

 

 

4                   Using Logic Tiles with the Emulation Baseboard

4.1             The Versatile family of boards

 

A Versatile system normally consists of:

·         A Versatile baseboard, such as the Emulation Baseboard. This board contains a bus matrix and a number of peripherals. On the board there is volatile and non-volatile memory, and also an FPGA.

·         One or more Logic Tiles or Core Tiles, which can be configured to implement hardwired logic, AHB peripherals or synthesizable cores.

 

The FPGA on the Emulation Baseboard interfaces external peripherals with four external buses:

·         AHB M1 is an external master bus, so the baseboard FPGA behaves as a bus master. The AHB M1 is connected to the baseboard FPGA and Logic Tiles on tile site 1.

·         AHB M2 is an external master bus, so the baseboard FPGA behaves as a bus master. The AHB M2 is connected to the baseboard FPGA and Logic Tiles on tile site 2.

·         AHB S1 is an external slave bus, so the baseboard FPGA behaves as a slave of the bus. The AHB S bus is connected to the baseboard FPGA and Logic Tiles on tile site 1.

·         AHB S2 is an external slave bus, so the baseboard FPGA behaves as a slave of the bus. The AHB S bus is connected to the baseboard FPGA and Logic Tiles on tile site 2.

 

The baseboard FPGA is based around an internal bus matrix.

·         The AHB M1 and M2 bridges inside the baseboard FPGA are slaves of the bus matrix, mapped at fixed addresses of the memory map.

·         The AHB S1 and S2 bridges are masters of the bus matrix, and have their own bus layer.

All masters (including external masters) have access to the M1 and M2 external buses. For details about what slaves can be accessed by each master, please see the Emulation Baseboard AHB documentation.

 

4.2             Emulation Baseboard buses: standard operation

In order to comply with the AHB specification, the slaves connected to a bus must respond to the whole range of addresses. A system with an Emulation Baseboard and one or more Logic Tiles this has the following implications:

·         The Logic Tile must respond to addresses 0x18000000 – 0x1FFFFFFF in bus M1

·         The Logic Tile must respond to addresses 0x80000000 – 0xFFFFFFFF in bus M2

Normally a default slave is used to respond to the addresses not mapped to real slaves. The default slave simply drives HREADY = 1 and HRESP = ERROR, so it generates an abort when it is accessed.

 

 

 

 

The example HDL code provided with this application note implements a standard system in a Logic Tiles, consisting of the following elements:

·         Slaves connected to bus M2 and mapped at address 0xC0000000. Addresses from 0x80000000 to 0xFFFFFFFF are mapped to bus M1 inside the baseboard FPGA, so these slaves are accessible from all the masters in the system.

·         Default slaves respond to accesses to other addresses in bus M2.

·         Any masters implemented in Logic Tiles are connected to bus Sx. These masters can access the resources inside the baseboard FPGA through the bus matrix, as well as those on buses M1 and M2.

 

Figure 4 shows a standard system in which the masters and slaves are synthesized in a Logic Tile.

The Logic Tile must respond to addresses 0x80000000 – 0xFFFFFFFF in bus M2

Image

Figure 4: Standard configuration of Emulation Baseboard plus Logic Tile on tile site 2 – flow from masters to slaves

 

The figure shows how masters connected to the AHB S2 bus can access slaves connected to the AHB M1 and AHB M2 buses through the bus matrix.

The figure also shows which signals of the header connectors are used to route the M2 and S2 buses:

·         AHB M2 is routed via HDRY: This bus is only connected to the Logic Tile at the bottom of the stack.

·         AHB S2 is routed via HDRX: This bus is only connected to the Logic Tile at the bottom of the stack.

 

An arbiter must be provided to arbitrate between the masters in the Logic Tile and the PCI master on the Emualtion Baseboard FPGA. This arbiter is embedded inside the bus matrix.

 

·         Sometimes the user may not need to synthesize AHB masters in the Logic Tile. In this case the masters and arbiter can be removed. The Logic Tile pins should be driven so that all the control signals are tied to generate idle transactions (HTRANS = 2’b00).

 

4.3             Emulation Baseboard buses: booting from AHB expansion bus

 

It is not possible to boot from the M1 or M2 buses on the Emulation Baseboard using the default AHB configuration. The Logic Tiles will only ever appear at 0x18000000-0x1FFFFFFF (M1) or 0x80000000 – 0xFFFFFFFF (M2).

 

4.4             Emulation Baseboard clocks

 

The Emulation Baseboard clock architecture is complex and highly configurable. The baseboard contains clock multiplexers, so that different clock signals can be used. The clock multiplexers can be configured so that the clocks are driven by either the baseboard or the Logic Tiles.

However the provided example design uses CLK_IN_MINUS1 as the master clock from the baseboard and is used as the clock frequency for all AHB logic inside the Logic Tiles.

5                   Description of the Example HDL

5.1             General description

Example Verilog code, synthesis scripts and pre-synthesized bit-files are provided with this application note. The example code shows how to implement AHB masters and slaves in a Logic Tile working in one possible configuration:

·         Configuration 1: Emulation Baseboard + Logic Tile (site2)

Note: the example design is loaded into Logic Tile IMAGE 0 (S10[4:1] on the EB all off).

The example design is based on the Example2 that used to be included on the logic module and Logic Tile installation disk. This example has been modified to support the configuration above.

The example design implements a simple AHB system. The original example2 only implemented AHB slaves, but AHB masters have also been added, resulting in the following example design:

·         Configuration 1 with AHB masters and slaves

 

The example design contains the following AHB slaves:

·         LT-XC2V4000+ and LT-XC5VLX330, two ZBT SSRAM controllers: give access to the Logic Tile SSRAM devices from the AHB bus.

·         LT-XC4VLX100+, two Block RAM controllers:  give access to the Logic Tile FPGA Block RAM from the AHB bus.

·         An AHB to APB bridge: gives access to the following APB peripherals

o        APB configuration registers

o        APB interrupt controller

·         A default slave

 

In a Versatile system the AHB slaves are connected to the AHB M2 bus. The Logic Tile interrupt is routed to the VIC inside the development chip as source number 40.

The example design includes two AHB masters. The two masters are identical and have very limited functionality, since they are only intended to show how to integrate existing AHB masters in a Logic Tile.

The example masters generate a transfer when the Logic Tile push button is pressed. The address of the transfer is programmed in Logic Tile registers. Which master generates the transfer and the type of transfer is selected by the Logic Tile switches.

The design with masters also includes an arbiter.

The Logic Tile also includes some miscellaneous logic to control the Logic Tile hardware:

·         A controller for the fold-over and thru switches

·         Three ICS307 clock controllers

·         Internal routing of the JTAG debug signals: D_TDI to D_TDO and D_TCK to D_RTCK

 

The example design works at up to 40MHz system bus clock on a Versatile system (NOTE the baseboard image will sometimes have a lower limit).

5.2             Description of the HDL

Below there is a general description of the source code files provided. All the files are supplied in Verilog (.v). Each file normally contains only one module of the same name, with the exception of APBClocks and APBClockArbiter.

AHBTopLevel: This file is the top level HDL, which instantiates and interconnects the main blocks in the system. It also includes the tri-state interface logic that gives access to the external bus or buses.

AHBDecoder: Generates the HSEL selection signals for the AHB slaves. These signals are generated with combinatorial logic from HADDR.

In the example code there are two decoder blocks, AHBDecoderM1 and AHBDecoderM2, one for each of the external master buses.

AHBMuxS2M: This module multiplexes the HREADY, HRESP, and HRDATA outputs from the AHB slaves. The outputs from the multiplexer are used to drive the tri-state buffers that access the AHB system bus.

AHBDefaultSlave: The HREADY and HRESP signals are driven by the default slave if the Logic Tile is accessed at an address not covered by any of the peripherals or memory in the design.

AHBAPBSys: The APB components are instantiated in this block. These include the AHB-APB bridge and the APB peripherals.

AHB2APB: This is the bridge that connects the APB peripherals to the internal AHB bus. It also produces the peripheral select signals for each of the APB peripherals.

APBRegs: The APB register peripheral provides memory-mapped registers.

APBIntcon: The APB interrupt controller contains the interrupt controller registers, which can accept up to four external interrupts and four software interrupts. The example code only uses one external interrupt, generated by the push button.

The example versions that implement masters also include the following files:

AHBExampleMaster: Implements a simple AHB master that generates a transfer when the Logic Tile push button is pressed.

AHBMuxM2S: Multiplexes the outputs from the masters depending on which one is granted the bus. The outputs from the multiplexer drive the tri-state buffers that give access to the system bus.

AHBArbiter: Arbitrates between the different masters in the system. It implements a round robin scheme with equal priority between the masters.

The LT-XC2V4000+ Virtex 2 and LT-XC5VLX330 Virtex 5 logic tile design includes the following files:

AHBZBSRAM: ZBT SSRAM controller that allows word, half-word, and byte access to the Logic Tile SSRAM from the AHB system bus. Two AHBZBTRAM modules are instantiated in the design, one for each SSRAM device on the board.

APBClocks: Provides a parallel to serial interface that transfers the APB clock register contents to the ICS307 clock generators.

APBClockArbiter: Implements a simple arbitration scheme to ensure that the three clock controllers are serviced independently.

The LT-XC4VLX100+ Virtex 4 logic tile design includes the following files:

ltxc4vlx100_serial: Provides the serial interface between the logic tile FPGA and PLD to allow control of on board clocks, fold/through switches, user LEDs and user switches.

AHB1Port1RAM.v: AHB to Block RAM memory controller to allows access to Block RAM memory from the AHB system bus.

AHBFSM.v: AHB Block RAM controller state machine.

ARM_64kx32_BRAM.v: FPGA block RAM configured as 64k * 32bit wide (256kB).

Figure 5 shows the structure of the example HDL. The boxes with dotted line are the modules that only appear in some of the configurations.

Image

Figure 5: Structure of the example HDL

 


5.3             Description of the masters

 

The example masters generate a single word access in the system bus when the Logic Tile push button is pressed.

The Logic Tile switch S1 selects which master generates a transfer and the type of transfer:

·         If S1-1 is OFF, master 0 generates the transfer

·         If S1-1 is ON, master 1 generates the transfer

·         If S1-2 is OFF, the enabled master generates a write transfer

·         If S1-2 is ON, the enabled master generates a read transfer

 

The addresses for the system bus accesses are programmed by writing to two new Logic Tile registers: HADDR_TRANSFER0 and HADDR_TRANSFER1.

·         HADDR_TRANSFER0 contains the transfer address for master 0 and is located at offset address 0x24

·         HADDR_TRANSFER1 contains the transfer address for master 1 and is located at offset address 0x28

The example contains two registers which are named for compatibility with previous examples. The registers called IM_LT1_LEDS and IM_LT1_SW are used to configure the transfers generated by the masters:

·         IM_LT1_LEDS at address offset 0x014 becomes HDATA_WRITE and is a read/write register. The register contains the data that will be written in the next write transfer.

·         IM_LT1_SW at address offset 0x20 becomes HDATA_READ and is a read-only register. This register contains the data read in the last read access.

 

For example, if you want master 0 to write the data 0x05 to address 0x04000010, you must follow these steps:

·         Set S1-1 to OFF, so master 0 generates the transfer

·         Set S1-2 to OFF, so the transfer is a write transfer

·         Write 0x05 to register HDATA_WRITE at address 0xC0000014

·         Write 0x04000010 to register HADDR_TRANSFER0 at address 0xC0000024

·         Push the Logic Tile push button

 

Due to the Versatile system architecture, the Logic Tile master can access the baseboard devices through the baseboard FPGA’s bus matrix. By default after reset, HADDR_TRANSFER0 and HADDR_TRANSFER1 are programmed to access the baseboard SDRAM.

·         HADDR_TRANSFER0 = 0x04000000

·         HADDR_TRANSFER1 = 0x04000004


5.4             Memory map

 

All the AHB and APB peripherals instantiated in the design can always be found at the same offset address. The example design responds to 256MB of addresses, for example from address 0xC0000000 to 0xCFFFFFFF. The base address for the Logic Tile peripherals depends on the configuration chosen and the position of the Logic Tile in the stack.

The offset for the different peripherals is shown in Table 1:

 

Device

Registers

Int. Controller

SSRAM 0

SSRAM 1

Default Slave

LT-XC2V4000+ offset

0x0

0x01000000

0x02000000

0x02200000

0x024000000

LT-XC4VLX100+ offset

0x0

0x01000000

0x02000000

0x02040000

0x024000000

LT-XC5VLX330 offset

0x0

0x01000000

0x02000000

0x03000000

0x024000000

Table 1: Offset address for peripherals in example design

All the slave peripherals are connected to AHB M2. The base address of the peripherals is fixed at 0xC0000000. The default slave responds to all the other addresses in the 4GB range.

5.5             System registers

Table 2 shows the location of the system registers in the example design. The addresses shown are offsets from the Logic Tile base address.

Offset address

Name

Type

Size

Function

0x00000000

LT_OSC0

Read/write

19

Oscillator 0 divisor register

0x00000004

LT_OSC1

Read/write

19

Oscillator 1 divisor register

0x00000008

LT_OSC2

Read/write

19

Oscillator 2 divisor register

0x0000000C

LT_LOCK

Read/write

17

Oscillator lock register

0x00000010

LT_LEDS

Read/write

4/81

User LEDs control register (LT)

0x00000014

IM_LT1_LEDS / HDATA_ WRITE

Read/write

82

User LEDs control register (IM-LT1) / Data to write next transfer

0x00000018

LT_INT

Read/write

1

Push button interrupt register

0x0000001C

LT_SW

Read

4/81

Switches register (Logic Tile S1)

0x00000020

IM_LT1_SW / HDATA_READ

Read

82

Switches register (IM-LT1 S3) / Data read last transfer

0x00000024

HADDR_TRANSFER0

Read/write

32

Address next transfer master 0

0x00000028

HADDR_TRANSFER1

Read/write

32

Address next transfer master 1

Table 2: Location of system registers

1 LT-XC2V4000+/LTXC4VLX100+ and LT-XC5VLX330 designs.

2 LT1_LEDS and LT1_SW registers do not connect to external devices in this design, see section 5.3


Oscillator divisor registers

The oscillator registers LT_OSC0, LT_OSC1 and LT-OSC2 (at offset 0x00, 0x04 and 0x08) control the frequency of the clocks generated by the three clock generators on the Logic Tile.

Before writing to the oscillator registers, you must unlock them by writing the value 0x0000A05F to the LT_LOCK register. After writing the oscillator register, relock it by writing any other value to the LT_LOCK register.

 

Bits

Name

Access

Function

Default

[18:16]

OD

Read/write

Output divider:

b000 = divide by 10

b001 = divide by 2

b010 = divide by 8

b011 = divide by 4

b100 = divide by 5

b101 = divide by 7

b110 = divide by 3

b111 = divide by 6

b000

[15:9]

RDW

Read/write

VCO divider word. Defines the binary value of the RV[6:0] pins of the clock generator

b0010110

[8:0]

VDW

Read/write

Reference divider word. Defines the binary value of the V[7:0] pins of the clock generator

b001110000

 Table 3: LT_OSCx bit pattern

 

The reset value of these registers sets the oscillators to 24MHz. More information about setting up the frequency of the Logic Tile oscillators is available in the LT-XC2V4000+ Logic Tile.

 

Oscillator lock register

The lock register LT_LOCK (at offset 0x0C) controls access to the oscillator registers and allows you to lock them and unlock them. This mechanism prevents the oscillator registers from being overwritten accidentally.

 

Bits

Name

Access

Function

[16]

LOCKED

Read

This bit indicates if the oscillator registers are locked or unlocked:

b0 = unlocked

b1 = locked

[15:0]

LOCKVAL

Read/write

Write the value 0xA05F to this field to enable write accesses to the oscillator registers.

Write any other value to lock the oscillator registers.

Table 4: LT_LOCK bit pattern

 

User LEDs control registers

The LT_LED register (at offset 0x10) controls the 4 user LEDs on the LT-XC2V4000+ Logic Tiles or 8 user LEDs on the LT-XC4VLX100+ and LT-XC5VLX330 Logic Tiles.

The IM_LT1_LED register (at offset 0x14) controls the 8 user LEDs on the IM-LT1 interface module. In configuration 1 (Emulation Baseboard example HDL), this register has been replaced – see Registers used by example masters below.

Writing a 1 to a bit lights the associated LED.

 

Push button interrupt register

The push button interrupt register LT_INT (at offset 0x18) contains 1 bit. It is a latched indication that the push button has been pressed. The contents of this register are fed to the interrupt controller registers.

 

 

Bits

Name

Access

Function

[0]

LT_INT

Read

Write

If the push button has been pressed, this bit is set.

Write b0 to this register to clear the latched push button indication.

Writing b1 to this register has the same effect as pressing the push button.

Table 5: LT_INT bit pattern             

 

Switch registers

Use the LT_SW register (at offset 0x1C) to read the setting of the 4-way DIP switch on the on the LT-XC2V4000+ Logic Tiles and the 8-way DIP switch on the LT-XC4VLX100+ and LT-XC5VLX330 Logic Tiles.

Use the IM_LT1_SW register (at offset 0x20) to read the setting of the 8-way DIP switch on the IM-LT1 interface module. In configuration 1 (Emulation Baseboard example HDL), this register has been replaced – see Registers used by example masters below.

A value 1 indicates that the associated switch element is CLOSED (ON).

 

Registers used by example masters

HADDR_TRANSFER0 contains the transfer address for master 0 and is located at offset address 0x24

HADDR_TRANSFER1 contains the transfer address for master 1 and is located at offset address 0x28

In configuration 3 (based on Versatile), the registers IM_LT1_LEDS and IM_LT1_SW are replaced with:

HDATA_WRITE contains the data that will be written in the next write transfers and is located at offset address 0x14.

HDATA_READ contains the data read in the last read transfers and is located at offset address 0x20.

 


5.6             Interrupt controller

 

The interrupt controller included in the example design generates an interrupt signal from a number of interrupt sources. The output of the interrupt controller is routed in a different way depending on the configuration used:

·         Configuration 1: the Logic Tile interrupt is routed to the primary interrupt controller inside the baseboard FPGA as interrupt source 40

 

The Logic Tile interrupt controller is designed so that it can accept up to four sources of interrupts and four software interrupts. In the example design only one source of interrupt is used, which is connected to the Logic Tile push button.

The other three sources or interrupt are unused in the example design, but users can use them to connect interrupt request signals for the peripherals they implement in the Logic Tile.

The interrupt controller contains registers to enable, disable and monitor the status of the different interrupt sources.

Table 6 shows the interrupt number assigned to each source of interrupt. Each interrupt source is associated with a bit number in the interrupt controller registers.

 

 

Bit

Name

Function

[7:5]

-

Spare (not used by the example image)

[4]

PBINT

Push button interrupt

[3:0]

SOFTINT[3:0]

Software interrupt generated by writing to LT_SOFTINT

Table 6: Interrupt register bit assignment

For example, in order to enable the push button interrupt you must set bit 4 of the interrupt enable register.

Table 7 shows the location of the interrupt controller memory mapped registers.

 

Offset address

Name

Type

Size

Function

0x01000000

LT_ISTAT

Read

8

Interrupt status

0x01000004

LT_IRSTAT

Read

8

Interrupt raw status

0x01000008

LT_IENABLE

Read

8

Interrupt enable

0x01000008

LT_IENSET

Write

8

Interrupt enable set

0x0100000C

LT_IENCLR

Write

8

Interrupt enable clear

0x01000010

LT_SOFTINT

Read/write

4

software interrupt

Table 7: Location of interrupt controller registers

 

The way that the interrupt enable, clear, status and raw status registers work is illustrated in Figure 6. This figure shows the control logic for one interrupt source, corresponding to one bit of all these registers.

 

Image

Figure 6: Interrupt controller internal design

 

nINT in the figure is the interrupt request output from the Logic Tile interrupt controller. This signal is activated when any bit of LT_ISTAT is set.

 

Interrupt status register

The status register LT_ISTAT contains the logical AND of the bits in the raw status register and the enable register.

Therefore a bit of the status register is 1 when its corresponding interrupt source is active and its corresponding interrupt enable bit has been set.

 

Interrupt raw status register

The raw status register LT_IRSTAT indicates the signal levels on the interrupt request inputs. A bit set to 1 indicates that the corresponding interrupt request is active.

 

Interrupt enable, interrupt enable set and interrupt enable clear

Reading from the interrupt enable register LT_IENABLE returns the current state of the interrupt source enable bits.

Writing b1 to a bit of the interrupt enable set register LT_IENSET sets the corresponding bit of LT_IENABLE

Writing b1 to a bit of the interrupt enable clear register LT_IENCLR clears the corresponding bit of LT_IENABLE

Writing b0 to a bit of LT_IENSET or LT_IENCLR leaves the corresponding bit of LT_IENABLE unchanged

LT_IENABLE and LT_IENSET share the same address in the memory map.

 


Software interrupt register

This register is used to generate interrupts by software.

Writing b1 to any bit position in LT_SOFTINT register sets the corresponding bit in the interrupt controller registers. The LT_SOFTINT register has four bits, corresponding to the four software interrupts.

Writing a b0 to this register clears any software interrupts.

Reading from this register shows the raw status of the software interrupts.

The software interrupts should not be confused with the ARM SWI instruction.

 

6                   Example software

Example software is provided to verify the example design and the logic tile hardware.

The source files included are logic.c, logic.h and rw_support.s. Logic.c contains the main code, written in C. rw_support.s contains several assembler functions to perform word, half-word and byte accesses to the ZBT SSRAM or FPGA Block RAM.

A batch file with calls to the compiler, assembler and linker, and a built image are also provided for each of the configurations. The software can be re-built with both ADSv1.2 and RVDSv2.1 or later.

 

After the FPGA is configured, as indicated by the FPGA_OK LED, you can download and execute the example software on any ARM processor in the system. For example the software can be executed by an ARM926EJ-S processor on a CT-GTC plugged on Tile Site 1 of the EB baseboard.

 

The example code communicates with the user via the debugger’s console window. It operates as follows:

1. Reads the baseboard identification register to ensure that the software is executed on the correct system.

2. Sets the logic tile clocks.

3. Flashes the LEDs on the logic tile.

4. Tests the logic tile push button and interrupt controller.

5. Tests the ZBT SSRAM/Block RAMs for word, half-word and byte accesses.

6. Test the User LEDs and Switches.

 

Copyright © 2007 ARM Limited. All rights reserved. ARM DAI 0146D
Non-Confidential