2.2.  Special Considerations

The way ARM720T rev4 cores drive the HPROT signals on the AHB imposes some restrictions when using the cache controller with ARM720T rev4 cores.

To ensure memory consistency when WT memory accesses are used, the cache controller must be forced to treat all cacheable memory accesses as WT, allocate on read miss.

Note

This approach still enables the write allocate override bit to be set in the Auxiliary Control Register. See L210 Auxiliary Control Register on page 2-9 of the L210 Technical Reference Manual.

This may cause problems if legacy software assumes WT with read allocate behavior, when WT with read-allocate and write allocate is possible.

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