3.1. ARM920T and ARM922T cores

This section describes how to use the L210 with the ARM920T and ARM922T processor cores.

General Connections

The ARM920 and ARM922T processor cores have a single ASB. These must be converted to AHB by using an ARM920/ARM922T AHB wrapper. The resulting single AHB interface should be connected to slave 1 of the L210. Therefore you should:

Tie off L210 Slave Port 0 and 2 pins

  • HBSTRBSx[7:0] must be tied HIGH

  • HPROTSx[4] must be tied to HPROTSx[3]

  • HPROTSx[5] must be tied LOW

  • HUNALIGNSx must be tied LOW

  • HRESPMx[2] must be tied LOW.

Tie off unused pins on slave ports 1

  • Read data is on HRDATA[31:0], and HRDATA[63:32] is always 0

  • Write data must be duplicated on HWDATA[63:32] and HWDATA[31:0].

Tie off unused pins on master port 1

  • Write data is on HWDATA[31:0], and HWDATA[63:32] is always 0.

  • Read data must be duplicated on HRDATA[63:32] and HRDATA[31:0].

Special Considerations

When using the cache controller with ARM920 or ARM922 cores the AHB wrapper for the ARM920 or ARM922 core maps some cacheable stores to being non-cacheable. Re-mapping logic is required between the AHB wrapper and the cache controller:

// Maps all cacheable reads and all bufferable writes// to WTHPROTSn[3] = HPROT[3] or HPROT[2]HPROTSn[2] = 1'b0

In addition you must write to L210 Debug Control Register, register 15, and set bit 1 to 1'b1. This forces the L210 to treat all cacheable accesses as WT, allocate on read miss. See L210 Debug Control Register on page 2-22 of the L210 Technical Reference Manual.

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