3.2. ARM926EJ cores (revisions r0p0-r0p5)

This section describes how to use the L210 with the ARM926EJ-S processor core and derivatives.

General Connections

The ARM926EJ-S has dual AHB ports. These should be connected to slaves 0 and 1 of the L210. Therefore you should:

Tie off L210 Slave Port 2 pins

  • HBSTRBSx[7:0] must be tied HIGH

  • HPROTSx[4] must be tied to HPROTSx[3]

  • HPROTSx[5] must be tied LOW

  • HUNALIGNSx must be tied LOW

  • HRESPMx[2] must be tied LOW.

Tie off unused pins on slave ports 0 and 1

  • Read data is on HRDATA[31:0], and HRDATA[63:32] is always 0

  • Write data must be duplicated on HWDATA[63:32] and HWDATA[31:0].

Tie off unused pins on master ports 0 and 1

  • Write data is on HWDATA[31:0], and HWDATA[63:32] is always 0.

  • Read data must be duplicated on HRDATA[63:32] and HRDATA[31:0].

Special Considerations

The way ARM926EJ cores drive the HPROT signals on the AHB imposes some restrictions when using cache controller with ARM926EJ cores.

When using the cache controller with ARM926EJ cores:

  • Before disabling the L1 cache, first clean and invalidate, and disable the cache controller cache.

  • All page tables must reside in a WT memory region.

  • ARM926EJ does not distinguish between WT and WB accesses at L2. By default the cache controller treats all cacheable accesses by ARM926EJ as WB. To ensure memory consistency when WT memory accesses are used, the cache controller must be forced to treat all cacheable memory accesses as WT.

    • To do this write to L210 Debug Control Register, register 15, and set bit 1 to 1'b1. This forces the cache controller to treat all cacheable accesses as WT, allocate on read miss. See L210 Debug Control Register on page 2-22 of the L210 Technical Reference Manual.

      If the above approach is not acceptable, it can be done in hardware by implementing a piece of logic between the ARM926EJ core and the cache controller to detect HPROT = WB and map it to HPROT = WT at L2. The following is an example:

      if (HPROT[3:2] == 2'b11)HPROTSn[3:2] = 2'b10; // WB mapped to WTelseHPROTSn[3:2] = HPROT[3:2]; // WT, NCNB, NCB unaltered
ARM926EJ-S ITCM and L210 incompatibility

A separate errata document deals with ARM926EJ-S ITCM and L210 Cache Controller incompatibility:

ARM926EJ-S DHPROT incorrect when the instruction TCM is accessed, ARM926EJ-GENC-003141

Copyright © 2006. All rights reserved.ARM DAI 0169A