4.1.  Recommended Approach: Use a v6 Memory System

Slaves within the v6 Memory System must be able to correctly interpret the v6 AHB Extensions. In most cases, slaves can very easily be adapted to ensure that they are v6 compliant.

HUNALIGN - this signal indicates that the access is unaligned or sparse (where some bytes are missing from the access). With the ARM7 and ARM9 processor cores connected to the L2CC slave ports, only writes will assert this signal, and when it is not asserted the slave can behave as normal (v5). When this signal is asserted, the slave must monitor other v6 signals to determine what is required.

HBSTRB - this bus indicates which of the byte lanes is valid. Since the L2CC will only assert HUNALIGN on buffered writes when connected to the ARM7 and ARM9 cores, this bus indicates which of the byte lanes contain real data to be written, and which do not (and thus, the byte in memory should not be updated).

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