4.2. Using the L2CC with a Byte Lane Strobe Converter and v5 Memory System

When connected to ARM7 and ARM9 processor cores, the L2CC will perform reads and non-buffered writes as straight AHB 2 accesses (HUNALIGN = 1'b0).

However, the write buffer in the L2CC is a merging buffer. Data from any number of writes on the same line (within an 8 word boundary) will be merged together into a single write from the L2CC. Because of the likelihood of sparse data within the write buffer, the L2CC performs all write buffer drains as unaligned (v6 AHB Extensions).

There is no way to switch off the merging capability of the write buffer within the L2CC.

As has already been mentioned, the L2CC can be used in an existing v5 Memory System by using a Byte Lane Strobe Converter. This block takes the v6 style outputs of the L2CC and converts the signals and accesses into a v5 style AHB.

What is the Byte Lane Strobe converter?

As supplied by ARM Ltd., the BLS Converter is an AHB master gasket module (i.e. it is not a bridge - it acts as a transparent converter), which converts v6 type AHB accesses to v5 type AHB accesses.

The BLS Converter appears to be transparent when the L2CC is performing standard v5 accesses (that is, when HUNALIGN is 1'b0), but when HUNALIGN is asserted intervenes and converts the possibly unaligned or sparse accesses to byte accesses. In a 32-bit system every full word access that is marked with HUNALIGN is converted to 4 byte accesses and hence the transfers using the BLS Converter decreases down to about ¼ speed.

Because the BLS has no visibility of the future, and because the L2CC can perform a seemingly v5 burst (aligned and complete) from its write buffer with HUNALIGN set high, using the L2CC with the BLS Converter and a v5 Memory System can reduce the efficiency of the system dramatically.

Copyright © 2006. All rights reserved.ARM DAI 0169A