1.4. Memory map

Unlike most previous ARM cores, the overall layout of the memory map of a device based around the Cortex-M3 is fixed. This allows easy porting of software between different systems based on the Cortex-M3. The address space is split into a number of different sections. This is shown in Figure 1 and described in Table 1.

Figure 1. Cortex-M3 memory map

Table 1. Details of Cortex-M3 memory map (continued)

Memory RegionDescriptionAccessed via bus
codeFor code memory (flash, ROM, or remapped RAM).ICode and DCode
SRAMFor on-chip SRAM with bit-banding feature.system
peripheralFor normal peripherals with bit-banding feature.system
external RAMFor external memory.system
external deviceMemory space for external peripherals or shared memory.system
private peripheralAddress space for system devices such as MPU, NVIC, DAP, and other CoreSight devices.system
vendor specificFor additional uses specified by the vendor..
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