2.2. Memory Protection Unit (MPU)

The Cortex-M3 includes an optional MPU. See the datasheets and other information from your silicon manufacturer to determine if an MPU is included.

MPU register locations

The MPU registers are located at 0xE000ED90. There are 5 basic MPU registers and a number of alias registers for each of the regions. Table 2 provides a brief overview of the MPU registers. See the Cortex-M3 Technical Reference Manual for further details.

Table 2. MPU Registers

MPU type0xE000ED90Contains the number of regions in bits [15:8] and 0 for no MPU.
control register0xE000ED94Controls enabling/disabling of the MPU, the use of the default memory map for privileged accesses and whether the MPU is enabled during Hard Fault, NMI and Fault Mask handlers.
region number0xE000ED98Selects the region you want to configure.
region base address0xE000ED9CSets or reads the base address of region.
region attribute and size0xE000EDA0Sets or reads the size and permissions of region.

There are also aliases of the region base address registers and region attribute and size register for each region. These follow the region attribute and size register directly. They are located at 0xE000EDA4 rising through memory sequentially. These are particularly useful for configuring the MPU quickly at power on, using STM instructions to write to the aliased addresses.

Configuring MPU regions

To configure an MPU region you must first select the region you want to configure. You can use one of two methods to do this. You can select the region by writing the appropriate value to the region number register. Another way to do this is to use bits 0 to 3 of the region base address register and set the VALID bit. With this second method you can also program the region base address into the region base address register at the same time.

When you have selected the region you must program the base address of the region. The base address value must be aligned to a multiple of the size of the region. So a 64KB region must be aligned on a multiple of 64KB, for example 0x00010000, 0x00020000 and so on.

Finally, you need to configure the permissions, size and enable the region using the region attribute and size register. See the Cortex-M3 Technical Reference Manual for details of the register layouts.


The MPU must be enabled by setting bit 0 of the MPU Control Register before any regions will be active.

Memory region attribute and size (types and access permissions)

The MPU supports a number of different memory types, extensions and attributes.These are configured for each region in the region attribute and size register. Table 3 provides details of the region attribute and size register.

Table 3. Region attribute and size registers

[28]XNInstruction access disable bit, 1= disable instruction fetches.
[26:24]APData access permissions, allows you to configure read/write access for User and Privileged mode.
[21:19]TEXType extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
[15:8]SRDSub-region disable field (see Sub-regions).
[5:1]REGION SIZERegion size of the region be configured, for example 4K, 8K.
[0]SZENABLERegion enable bit.

For full details about these fields see the Cortex-M3 Technical Reference Manual.


Each memory region is divided into eight sub-regions that can be individually disabled without affecting the rest of the region. Each sub-region is one-eighth of the main region and can be disabled using the SRD fields in the region attribute and size register. The lowest bit of the SRD field disables the sub-region with the lowest address.

Sub-regions are useful for overlapping memory regions, for example, if you have a large region but would like different attributes for a small section of it. A sub-region in the larger region could be disabled and a second MPU region used for that sub-region to provide the required attributes.


Sub-regions cannot be used on regions of size 32, 64 and 128 bytes.

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