2.4. Instruction set support

There are a number of instructions supported by the Cortex-M3 that the compiler cannot generate by itself, as these normally have a specific use and their function is not easily expressed in the C language. However these instructions can still be used either through the assembler, compiler intrinsics, or embedded assembly.


More detail on the following instructions and the full instruction set can be found in the RVCT Assembler Guide or ARM Architecture Reference Manual.

Memory access instructions

The main memory instructions that the compiler cannot generate directly from C code are the load and store exclusive instructions, LDREX and STREX. These are used to perform exclusive memory accesses, for example to provide mutexes between different threads.

Barrier instructions

The Cortex-M3 supports a number of barrier instructions. These can be used to ensure the completion of certain events before starting the next instruction or event.

The Instruction Synchronization Barrier (ISB) flushes the pipeline in the processor, so that all instructions following the ISB are fetched from cache or memory, after the instruction has been completed. It ensures that changes to the system, for example the MPU, take immediate effect.

The Data Synchronization Barrier (DSB) acts as a special kind of memory barrier. The DSB operation will complete when all explicit memory accesses before this instruction have completed. No instructions after the DSB will be executed until the DSB instruction has completed, that is, when all of the pending accesses have completed.

The Data Memory Barrier (DMB) acts as a memory barrier. It has slightly different behavior to DSB. The DMB instruction will ensure that any memory accesses before the DMB have completed before any memory access from instructions following the DMB instruction are performed.

Example 8 shows a fragment of typical MPU code to show how these barrier instructions are used. This involves creating small functions using the embedded assembler, each containing a single barrier instruction. These functions can later be inlined by the linker.

Example 8. Demonstration of barrier instructions using pseudo-intrinsics

/* pseudo_intrinsics.c */
/* Small embedded assembly functions for barrier instructions*/
/* Link with armlink --inline ... */

__asm void __ISB(void){    ISB    BX lr}__asm void __DSB(void){    DSB    BX lr}/* scs.c - Initialize System Control Space registers */void SCS_init(void){    /* Code to configure the MPU regions inserted here    …    */
    /* Enable the MPU */    SCS.MPU.Ctrl |= 1;

    /* Force Memory Writes before continuing */    __DSB();
    /* Flush and refill pipline with updated permissions */    __ISB();}

Conditional execution

Unlike ARM instructions, most Thumb instructions are unconditional. Thumb-2 adds three conditional instructions in addition to the 16-bit conditional branch provided in the Thumb-1 instruction set. These are:

  • A 32-bit conditional branch. This has an improved branch range of +/- 1MB.

  • 16-bit compare and branch on zero (CBZ) and compare and branch on non-zero (CBNZ) instructions, with a branch range of +4 to +130 bytes. For example, this can be generated for C code to branch out of a loop when counting down to zero.

  • A 16-bit if-then (IT) instruction. The IT instruction can be used to make up to four following instructions conditional. This is the instruction used most often in place of conditional execution, for example in a short if statement.

The assembler can automatically generate appropriate IT instructions in place of a conditionally executed instruction. This is particularly useful when porting legacy ARM-based code to the Cortex-M3.

System “hints”

There are a number of “hint” instructions that can be used to direct the core to perform an operation if it is supported by your implementation. The instructions only provide an indication to the core and do not force the core to do as instructed. Some or all the hint instructions will execute as a NOP if they are not supported by your device. Table 4 summarizes the hint instructions available in the Cortex-M3.

Table 4. Hint Instructions

WFEWait For EventIndicates to the processor to enter low power mode and wait for an event before waking. This requires no software intervention when woken.
WFIWait For InterruptIndicates to the processor to enter low power mode and wait for an interrupt before waking. This requires no software intervention when woken.
SEVSend EventSends an event to all processors in a multi-processor system.
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