3.1. General code modifications

Most platform-independent sections of your code will usually work correctly on the Cortex-M3 without modification. However, there are certain features of the code that you might need to modify and update for the new target.

Modifications to C code

When migrating a project from an ARM7 core to the Cortex-M3, you must recompile all of your C code for Thumb-2 with an appropriate --cpu option as described in Compiler and Assembler Options. This includes any third-party libraries.

Legacy Thumb-1 code is binary compatible with the Cortex-M3, and such code can be run on the new processor. However, in RVCT 3.0 the linker cannot protect you from accidentally linking object files and libraries that contain some ARM instructions. It is recommended that all code is recompiled for Thumb-2 if at all possible. If you need to use legacy objects or libraries, you must manually check that no ARM instructions are included in the linked image. If you have third-party libraries that are targeted at an ARM7, you might need to contact your supplier for a Thumb-2 version of their library.

The source code itself might also require some minor changes. In particular, statechanging pragma directives (#pragma arm and #pragma thumb) no longer apply and must be removed. Inline assembly code does not support compilation for Thumb-2, therefore such code must be rewritten using C, C++ or embedded assembly code.

Modifications to assembly code

Special care should be taken when porting assembly code.

If present, directives that cause assembly of ARM instructions (ARM or CODE32) must be removed or changed to THUMB in every case. Most existing code should then assemble without difficulty if you ensure that you provide the correct --cpu option on the assembler command line. However, some rare instructions that are supported by the ARM instruction set and not the Thumb-2 instruction set might need modification.

If any CODE16 directives are present, be aware that these will assemble without warning if changed to THUMB, although there might be subtle differences in behavior. This is because CODE16 assembles according to the legacy Thumb-1 syntax rules. For example, under the CODE16 syntax rules many instructions without an S suffix will encode to flag-setting variants. Under the syntax rules of the THUMB directive the S suffix must be explicitly specified.

The assembler will insert IT instructions as necessary for instructions that are to be conditionally executed. For example, a single ADDSNE r0, r0, r1 instruction (followed by an unconditional instruction) would become: IT NE followed by ADDS r0, r0, r1.

Be careful of core-specific and architecture-specific instructions. These include:

  • Co-processor instructions.

  • State or mode changes and other accesses to the PSR.

  • The SWP instruction, which has been replaced by LDREX and STREX.

  • Some addressing modes that are not supported by LDM and STM instructions.

  • Some other instructions that have additional restrictions in Thumb-2, for example LDR and STR instructions with a register offset and an immediate shift.

You might need to rewrite these portions of your code to cater for the programmer’s model of the Cortex-M3. The assembler will generate a warning or error if it finds any incompatibilities. Remember that most status and control registers are memory-mapped in the Cortex-M3 and that the supported modes are very different from an ARM7TDMI. Any code which changes state or mode must be modified if appropriate or removed. Likewise, code which accesses co-processors must be removed, unless this will be emulated by a handler for the Usage Fault exception.

Also beware of code which uses the value of the PC in address arithmetic. Because Thumb-2 uses mixed 16- and 32-bit instructions, the value of the PC is always the address of the current instruction plus 4 when used in a data processing operation.

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