3.3. Changes to Exception Handling

Your exception handlers must be adapted for the Cortex-M3.

You will not normally need a low-level handler in assembly language, because reentrancy is handled by the core. If your low-level handler performs additional work, you might need to split some of this into separate functions which can be called from the new handlers.Remember to mark your IRQ handlers using the __irq keyword for clarity and to ensure that the compiler can maintain the stack alignment for Cortex-M3 revision 0 hardware.

The Cortex-M3 has no FIQ input. Any peripheral that signals an FIQ on the ARM7TDMI project must be moved to a high-priority vectored interrupt, or to the NMI signal of the Cortex-M3. You might need to check that the handler for this kind of interrupt does not expect to use the banked FIQ registers, as these will now need to be stacked as for another normal IRQ handler.

Finally, you must write a new initialization function to configure the NVIC including the interrupt priorities. Interrupts can then be enabled before entering your main application code.

Critical sections and exception behavior

On the Cortex-M3, exception prioritization, nesting of exceptions, and saving of corruptible registers is handled entirely by the core to provide very efficient handling and minimize interrupt latency. This means that interrupts remain enabled by the core on entry to every exception handler. In addition, if interrupts are disabled when returning from an exception they will not be automatically re-enabled by the processor. It is not possible to perform an atomic enabling of interrupts and return from an exception. If you have disabled interrupts temporarily in your handler, they must be re-enabled first and then a separate instruction used to return. Exceptions might therefore occur immediately before the exception return.

These features of the exception model might impact on critical sections in the code, depending on the system design. Critical sections are those that require interrupts to be disabled for the duration of their execution so that they are executed as an uninterruptible block, for example the context switching code in an operating system. Certain legacy code might make assumptions that interrupts will be disabled on entry to exception handlers and will only be enabled explicitly by the code once any critical sections have been completed. These assumptions do not hold under the new exception model of the Cortex-M3, and such code might need to be rewritten to take account of this.

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