4. Debugging with the Cortex-M3

The Cortex-M3 provides sophisticated debug capabilities. These include:

In addition, the structure of the processor means that debug accesses are performed through a Debug Access Port (DAP). This is connected to the rest of the system, including the core, through the bus matrix. This means that you can carry out certain debug operations while the core itself is still running, if this is supported by your debugger. For example, you do not need to stop the core to be able to read from or write to external memory. This functionality is supported by RVD 3.0 when connecting to a hardware target. However, RVD 3.0 does not support the trace features of the Cortex-M3.

RVDS 3.0 also includes an Instruction Set System Model (ISSM) of the Cortex-M3. This provides simulation of the core, NVIC and other key features of the processor. It also models one UART peripheral and three additional timer peripherals. However, the model only simulates the breakpoint and watchpoint debug logic. The trace components are not modeled.

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