1                Introduction

1.1           Purpose of this application note

This application note covers the operation of the Emulation Baseboard (EB) with a CT-R4F. It examines the contents of the baseboard FPGA, the system interconnect, the clock structure, and specifics of the programmer’s model directly relevant to Core Tile operation.

After reading this Application Note the user should be in a position to make changes to the provided baseboard FPGA design, add their own AHB or AXI based peripherals to it, or debug and analyze the operation of the provided images.

1.2           EB and CT-R4F Tile overview

This application note is designed for a CT-R4F Tile fitted to Tile Site 1 on the EB as shown in Figure 1‑1 Core Tile and EB system. This application note only works with CT-R4F. The FPGA image for the baseboard is provided as part of the Versatile CD installation.

Figure 1‑1 Core Tile and EB system

1.3           Optional Logic Tile

One or more logic tiles can be fitted to Tile Site 2. These Logic Tiles can contain both additional masters and slaves. See application note AN151 for an example and information about how to do this.

2                Getting started

Before you can use this application note, you will need to program the EB with the required FPGA image to enable the CT-R4F to function correctly. Follow these steps to program the FPGA image.

1.    Plug the CT-R4F Tile onto TILE SITE 1 of the Emulation Baseboard.

2.    Slide the CONFIG switch (S1) to the ON position.

3.    Connect RVI to the Emulation Baseboard JTAG ICE connector (J18), or a USB cable to the USB Debug Port (J16).

4.    Check the external supply voltage is +12V (positive on center pin, +/-10%, 35W), and connect it to the power connector (J28).

5.    Power-up the boards. The '3V3 OK' LED and ‘5V OK’ on the Emulation Baseboard should both be lit.

6.    If using the USB connection, ensure that your PC has correctly identified an ARM® RealView™ ICE Micro Edition device is connected to the USB port. If the Windows operating system requires a USB driver to be installed please refer to the EB or PB926 \boardfiles\USB_Debug_driver\readme.txt.

7.    If using Real View ICE (RVI), you must ensure that the RVI unit is powered and has completed its start-up sequence (check the LEDs on the front panel have stopped flashing).

8.    You can now run the relevant ‘progcards’ utility for the connection you have prepared above.

·      progcards_usb.exe for your USB connection

·      progcards_rvi.exe for your RealView ICE connection

When using RVI select the target RVI box you are using.

9.    Select the option for CT-R4F. The utility will report its progress. It may take several minutes to download. A successful configuration download will be terminated with the message “Programming Successful”.

10. Power off the boards.

11. Set the configuration switches to load FPGA image 0. (S10 on the Emulation Baseboard set to all OFF).

12. Slide the CONFIG switch to the OFF position, and power on the boards. Ensure GLOBAL_DONE (D35) and the ‘POWER’ (D1) LEDs are lit. The Character LCD should show the Firmware and Hardware versions indicating that the Boot monitor firmware is running.

13. The system will now be fully configured and ready for use.

For configuring RVI for CT-R4F and AN217 debugging please refer to Using_CT-R4F_with_RVI.pdf file.  

3                Architecture

This application note implements an AXI (AMBA 3.0) based system on the EB FPGA. The EB image exposes two master ports and two slave ports (all 64 bit muxed AXI). There are one slave port and one master routed to tile site1 and one slave and one master port routed to tile site 2.

Note that the direction of the arrows indicates the direction of control: it points from the Master to the Slave. An AXI bus contains signals going in both directions.

The PCI core is not included in the build as it is third party IP, it is an optional component.

3.1           System overview

Figure 3‑1 System interconnect

3.2           System architecture

Figure 3‑2 AN217 example design block diagram

3.2.1        EB Module functionality

The function of each of these blocks is as follows:

AXI SYNC SLICE

This is a synchronous register slice that is added to the incoming master ports R4FM, CLCD, PCI, and DMAC on the bus matrix to ensure that data is available for a complete cycle prior to AXI matrix address decoding. It also helps to increase the operating frequency.

AXI ASYNC SLICE

This is an asynchronous bridge that is added to the incoming master port from tile site 2 to ensure that data is available for a complete cycle prior to AXI matrix address decoding and allows that site to operate in a different clock domain. It increases the operating frequency and introduces one clock cycle of latency.

AXI DEMUX

This block demultiplexes the multiplexes signals from the master ports on tile site 1 and 2. The muxing scheme is described in a section Error! Reference source not found..

ID COMPRESS

This block merges the ID fields on the AXI bus to reduce the width of each ID channel. The ID is compressed using a simple algorithm to save pins.

AXI MUX

This block multiplexes the signals from the master port Mp4. The muxing scheme is described in a section Error! Reference source not found. Error! Reference source not found..

64-bit AXI 6x6 Bus Matrix

This provides the bulk of the interconnect structure. It allows any of the 6 slave ports to connect to any of the 6 master ports without blocking the other masters. It also contains the decoder mapping to determine the address map, and a scheme to determine priority of competing masters to a single slave.

SSMC

This is a Synchronous Static Memory Controller. ARM PrimeCell PL093 is used in this design. For more information please refer to the PrimeCell documentation.

AHBtoAXI BRIDGE

This is a bridge component to change from an AHB bus to an AXI bus. Where nn is the input width and mm is the output width in decimal.

DMC

This is a Dynamic Memory Controller. ARM PrimeCell PL340 is used in this design. For more information please refer to the PrimeCell documentation. The default frequency for the DMC is 55MHz (OSCCLK1 divided by 2)

Since the Dynamic Memory Controller connects to high speed double data rate clocked devices it is necessary to make use of special pad and signal types to and from the Dynamic Memory. This block instantiated within the DMC

AXItoAPB BRIDGE

This is a bridge component to change from an AXI bus to an APB3 bus. This component contains decoding scheme for the bus, allowing 25 APB peripherals to be connected.

DMA

This is a direct memory access component. This design allows for the PrimeCell PL081 controllers to be added. It also allows for no DMA. For more information on the DMA blocks refer to the PrimeCell documentation.

PCI

The ARM provided image includes the option of including a Xilinx PCI component (version 3.0). This is a 32-bit wide PCI component, and operates at 33MHz. Refer to the EB Users Guide for further information.

CLCD

This is a color liquid crystal display controller. ARM PrimeCell PL111 is used in this design. For more information please refer to the PrimeCell documentation.

SYSTEM REGS

This contains a set of APB registers for hardware control of the EB. For a complete list of the functionality of these registers refer to the EB user guide.

SYSTEM CONTROL

This contains a generic set of system control registers. ARM ADK component SP810 is used in this design.

SERIAL BUS I/F

This is a controller for the serial bus to the PISMO and Time of Year clock.

AACI

This is an advanced audio codec interface. ARM PrimeCell PL041 is used in this design. The FIFO is increased in size from the standard to better suit the FPGA operating environment (lower bus frequency). For more information please refer to the PrimeCell documentation. This block instantiates Xilinx block rams.

MCI

This is the multimedia card interface. ARM PrimeCell PL181 is used in this design. For more information please refer to the PrimeCell documentation.

MOUSE

These are keyboard and mouse interfaces. ARM PrimeCell PL050 is used in this design. For more information please refer to the PrimeCell documentation.

CHARACTER LCD

This is a character LCD display interface. It allows the system to communicate with the character LCD display fitted to the baseboard.

UART0-3

These are universal asynchronous receiver-transmitter interfaces (RS-232 serial). ARM PrimeCell PL010 is used in this design. For more information please refer to the PrimeCell documentation.

SSP

This is a synchronous serial port. ARM PrimeCell PL022 is used in this design. For more information please refer to the PrimeCell documentation. This block instantiates Xilinx block rams.

SCI

This is the smart card interface. ARM PrimeCell PL131 is used in this design. For more information please refer to the PrimeCell documentation.

WATCHDOG

This is a watchdog controller. It allows for the generation of an interrupt or reset after a defined time, to prevent against system lockup/failure. ARM ADK component SP805 is used in this design.

TIMERS 0-3

These are timer modules. ARM ADK component SP804 is used in this design.

GPIO 0-2

These are general purpose input/output modules. ARM PrimeCell PL061 is used in this design. For more information please refer to the PrimeCell documentation.

REAL TIME CLOCK

This is a real time clock module. Real time refers to total time from an event, and not actual real world time (measured using the Time Of Year Clock). ARM PrimeCell PL031 is used in this design. For more information please refer to the PrimeCell documentation.

PCI CONTROL REGS

This is the PCI control block. This contains a set of registers to allow configuration of the PCI system (if used). See the programmer’s reference section for more information on the functionality of these registers.

3.3           Clock architecture

The clock architecture is carefully designed to minimize the skew (difference) in the clock edge position between different components across the system. The User Guides for all the boards used in this configuration explain the clock options.

Figure 3‑3 Clock architecture

There are 6 clock domains in this design:

3.3.1        EB Internal AXI System Bus and CPU External System Bus

The EB Internal AXI System Bus is clocked by ACLK. ACLK is generated from T1_CLK_BUF_LOOP through a clock buffer from OSCCLK0.

The CPU External System Bus is clocked at the same speed as the EB Internal AXI System by CLK_IN_MINUS1 input clock also generated from OSCCLK0 through a clock buffer.

3.3.2        DDR_CLK

OSCCLK1 is the source for all the DMC clocks: MCLK, MCLK90, and FBMCLK. It is divided by 2 to delivery MCLK and divided by 2 and half cycle deleted to delivery MCLK90 clock.

3.3.3        LT System Bus

The LT External System Bus is clocked by OSCCLK2.

The LT Internal System Bus in this diagram is the same frequency as the LT External System Bus. (LT Internal System Bus = LT External).

3.3.4        EB Internal and External Synchronous Static Memory Bus

The SMCLK is used to drive Synchronous Static Memory Controller and Static Memory bus peripherals. The SMCLK is directly connected to OSCCLK3.

3.3.5        CLCDCLK

CLCDCLK is directly connected to OSCCLK4.

3.3.6        CPU Internal Buses

The CPU Internal AXI System Bus clocks domains includes the R4F CPU domain, the DMA Controller, internal matrix domain, DMC domain and CLCD domain. The default behavior is for the ACLK PLL in the test chip to multiply the Core Tile input clock by 5 to drive R4F CPU clock domain. The DMA Controller and internal matrix domain is by default clocked by half of frequency of R4F CPU clock domain. The MCLK PLL in the test chip is used only to minimize the skew for DMC clock domain.

3.3.7        Default operating frequencies

Table 3‑1 Default operating frequencies

3.3.8        EB Clock Configuration Switch

A switch SW8.5 is used to select EB dynamic memory clock and static memory bus clock frequency to make it easy to set the clock for most customers.

SW8.5 – sets the DMC clock frequency by changing OSCCLK1 and SMC clock frequency by changing OSCCLK3.

Table 3‑2 Clock selection on EB

This switch is only sampled at the initial power up, and it is still possible to set any clock frequency in software using the EB SYS_OSCRESETx registers.

3.4           CT-R4F reset structure

Figure 3‑4 CT-R4F reset routing

Table 3‑3 CT-R4F Reset Signals

Figure 3‑5 Reset sequence

Figure 3‑6 Power-on reset timing

Figure 3‑7 Reset timing

3.5           Interrupt architecture

The interrupt scheme makes use of multiple Interrupt Controllers to facilitate the connection of an IRQ and FIQ to both tile sites, which would allow the connection of a second Core Tile on the EB tile site 2. Both tile sites can generate sources of interrupts and receive interrupts generated by the interrupt controllers.

Figure 3‑8 Interrupt architecture

A GIC (Generic Interrupt Controller) is chosen for this design, as it accepts a large number of interrupt sources without cascading interrupt controllers.

The all of interrupts are common to all four GICs.

A VIC (Vectored Interrupt Controller) implemented in R4F TC is by default bypassed and R4F processor IRQ and FIQ inputs are driven directly by EB GICs.

For a mapping of the 47 interrupt sources onto the 64-bit GIC interrupt input refer to the Emulation Baseboard User Guide. The memory mapping of the GICs is also shown in the User Guide.

4                Hardware Description

4.1           EB Top Level (EBFpga.v)

The top level of the design is of particular importance for a number of reasons. This level defined the clock structure, tri-state buffers and pull-up and pull-down resistors.

4.2           EB AXI Subsystem (EBFpgaCTR4F.v)

This level connects all the components together and ties off static pins. This includes all the major blocks as shown in Figure 3‑1 System interconnect.

4.3           EB AXI bus multiplexing (R4F_demux.v, T2_demux.v)

This level contains multiplexing and demultiplexing modules and defines the mapping from the HDRX, HDRY and HDRZ busses from the tile site into their functional allocations. The R4F_demux.v contains multiplexing and serial stream controller for CT-R4F and the T2_demux.v contains multiplexing for Tile 2.

By using a 2:1 multiplexer and registers scheme as shown below on Figure 4‑1 AXI multiplexing scheme it is possible to reduce the pin count for the AXI bus into a realistic size for implementation on the only Tile X header.

Figure 4‑1 AXI multiplexing scheme

The output data is multiplexed on the level of ACLK, to generate the multiplexed bus (X and Y). The de-multiplexing is performed by registering the data (A) generated on the high level of CLK when CLK goes low (DeMuxReg). The data (B), generated on the low side of CLK is passed straight. This design assumes data is always generated and captured on the rising edge of CLK.

The READY signals on AXI can not be multiplexed in this way due to their timing requirements and must be passed directly between devices.

The CT-R4F has implemented the multiplexing and de-multiplexing logic within the R4F TC. The EB baseboard has implemented the multiplexing and de-multiplexing logic within the FPGA using DDR registers.

The following timing diagram (see Figure 4‑2 AXI timing requirements) shows the data flow from FPGA to TC through the design with expected delays.

Figure 4‑2 AXI timing requirements

4.54.4  CT-R4F and AXI (AMBA 3) pin allocation differences

A number of signals from the R4F test chip differ from the generic Tile header pin allocation. These signals will be connected to the Z headers along with serial PLD control signals as show on Table 4‑1 Z bus signals.

Table 4‑1 Z bus signals

4.5           Header HDRX and HDRY AXI pin allocation

The four AXI buses (T1X, T1Y, T2X, T2Y) connect to the HDRX and HDRY Tile headers. The pin connections are the same for all four buses. T1X is shown as an example on Table 4‑2 Header HDRX and HDRY AXI pin allocation.

Table 4‑2 Header HDRX and HDRY AXI pin allocation

4.6           CT-R4F configuration PLD

The CT-R4F Tile contains a configuration PLD (see Figure 4‑3 CT-R4F configuration PLD) which defines:

·                   R4F testchip initialization signals

·                   R4F testchip resets

·                   Profile and status of the phase control logic

·                   ADC control.

A serial data stream from the FPGA on the EB below is used to configure the PLD settings after power up.

Figure 4‑3 CT-R4F configuration PLD

4.7           CT-R4F configuration PLD serial interface

Serial control of the configuration PLD is achieved through a three wire interface (see Figure 4‑4 CT-R4F configuration PLD serial interface). Reset signal PLDRESETn is also used to ensure the PLD logic is in the defined state before the data stream is loaded.

Figure 4‑4 CT-R4F configuration PLD serial interface

All data bits are clocked into the PLD on the rising edge of PLDCLK.

4.8           Serial data register

The serial interface is designed to mimic a memory mapped peripheral in that data sent to PLD has an address and data phase. This solution allows for an optimized logic implementation in the PLD and speeds up access to TC serial stream via the PLD.

The first bit of the input serial data contains the direction of the transaction. The followed 13 bits contain the address and the next 32-bits the data to be written to that address. The PLD serial data out contains Board ID, PLLs lock signals and the data from the selected address.

Table 4‑3 CT-R4F serial configuration interface data

Serial stream accessible registers:

Table 4‑4 CT-R4F serial configuration registers

4.9           CT-R4F power-up configuration

Following EB FPGA initialization a serial data controller reads BOARD_ID and CT_R4F_PLD_ID register from CT-R4F PLD using serial interface to recognise CT-R4F board. The serial data controller then transfers values of the EB FPGA CT_R4F_TC_CFGx and CT_R4F_OSCx registers and CT-R4F PLD configures R4F TC and on board oscillators.

After that the serial data controller constantly reads CT_R4F_ADCx registers to update PLLs lock status and CT_R4F_ADCx registers implemented on the EB FPGA. If any changes of CT_R4F_OSCx registers value are detected the new value is transferred to PLD.

Please refer to the CT-R4F User Guide for more R4F configuration process and timing details.

4.10       CT-R4F status LEDs

The two status LEDs D1, D2  indicate the status of the PLL lock signals and serial interface as follows:

Table 4‑5 Status LEDs

The status of LED is ON when signal is LOW and OFF when signal is HIGH.

4.11       EB CT-R4F specific registers

Setting of the R4F TC serial configuration registers, CT-R4F oscillators and CT-R4F PLD control registers is possible through the EB system registers.

The CT register base is 0x10000000. All registers must be unlocked by writing 0xA05F to base+0x20 first.

Table 4‑6 CT_R4F specific registers

The registers values are passed to/from CT-R4F PLD via Serial Stream Controller implemented on EB FPGA. The CT_R4F_x_ID, CT_R4F_OSCRESETx, CT_R4F_TC_CFGx registers values are passed to/from PLD only during CT initialization. The CT_R4F_OSCx, CT_R4F_DVI and CT_R4F_CTRL registers values are sent to CT after register update. The CT_R4F_ADCx read registers are constantly updated by serial stream controller.

4.11.1     CT_R4F_OSCx and CT_R4F_OSCRESETx registers

The input reference frequency to all oscillators is 24MHz. For more information on the ICS307 oscillator settings please see the ICS307 web site.

The CT_R4F_OSCRESETx registers are maintained through reset and can be used to load the oscillator after reset.

The CT_R4F_OSC0 register at base+0x110 on EB board sets the R4F internal ACLK frequency.

Table 4‑7 CT_R4F_OSC0 register

The CT_R4F_OSC1 register at base+0x114 on EB board sets the R4F SDRAM frequency.

Table 4‑8 CT_R4F_OSC1 register

The CT_R4F_OSC2 register at base+0x11C on EB board sets the R4F CLCD frequency.

Table 4‑9 CT_R4F_OSC2 register

The CT_R4F_OSCRESET0 register at base+0x120 on EB board sets the R4F internal ACLK frequency after reset.

Table 4‑10 CT_R4F_OSCRESET0 register

The CT_R4F_OSCRESET1 register at base+0x124 on EB board sets the R4F SDRAM frequency after reset.

Table 4‑11 CT_R4F_OSCRESET1 register

The CT_R4F_OSCRESET2 register at base+0x12C on EB board sets the R4F CLCD frequency after reset.

Table 4‑12 CT_R4F_OSCRESET2 register

4.11.2     CT_R4F_TC_CFGx registers

The CT_R4F_TC_CFGx registers are 32bits wide and contain the values for three R4F TC configuration words.

The CT_R4F_TC_CFG0 register at base+0x74 on EB board sets the R4F initial PLLs settings.  

Table 4‑13 CT_R4F_TC_CFG0 register

The CT_R4F_TC_CFG1 register at base+0x78 on EB board sets the R4F initial settings.

Table 4‑14 CT_R4F_TC_CFG1 register

The CT_R4F_TC_CFG2 register at base+0x7C on EB board sets the R4F initial settings.

Table 4‑15 CT_R4F_TC_CFG2 register

4.11.3     CT_R4F_ADCx registers

The CT_R4F_ADCx registers are 12 bits wide and all have the same following format.

The CT_R4F_ADC0 register at base+0xA0 board reads the Cortex R4 current.

Table 4‑16 CT_R4F_ADC0 register

The CT_R4F_ADC1 register at base+0xA4 board.

Table 4‑17 CT_R4F_ADC1 register

The CT_R4F_ADC2 register at base+0xA8 board reads the VSoc current.

Table 4‑18 CT_R4F_ADC2 register

The CT_R4F_ADC3 register at base+0xAC board reads the Core voltage.

Table 4‑19 CT_R4F_ADC3 register

The CT_R4F_ADC4 register at base+0xB0 board reads the PLL voltage.

Table 4‑20 CT_R4F_ADC4 register

The CT_R4F_ADC5 register at base+0xB4 board reads the IO voltage.

Table 4‑21 CT_R4F_ADC5 register

4.11.4     CT_R4F_DVI register

The CT_R4F_DVI register at base+0x13C controls DVI interface on the CT-R4F board.

Table 4‑22 CT_R4F_DVI register

4.11.5     CT_R4F_CTRL register

The CT_R4F_CTRL register at base+0x140 controls board level functions on the CT-R4F board.

Table 4‑23 CT_R4F_CTRL register

5                Programmer’s Model

5.1           CT-R4F boot up operation overview

This section is intended as a summary of the boot operation, please refer to the R4F Test Chip TRM for more information on the use of CP15 registers and exact operation.

5.2           R4F TC Memory Map

The CT-R4F on EB example design is in REMAP_MODE = 0.

Please refer to the CT-R4F User Guide for more R4F Test Chip memory map information.

5.3           EB Memory Map

The CT-R4F on EB example design provides a software interface with the majority of features required for a system. Refer to the EB user guide for more information