4.5. Enabling Interrupts using NVIC

Normally NVIC operations do not require the use of memory barrier instructions.

Example 3 shows example NVIC operations code.

Example 3. NVIC operations code

device_config(); 		// Setup peripheral
NVIC_ClearingPending(device_IRQn); // clear pending status
NVIC_SetPriority(device_IRQn, priority); // set priority level
NVIC_EnableIRQ(device_IRQn); // Enable interrupt


Note

Interrupts can enter pending state before they are enabled.

Architecturally, each SCS access has DMB behavior with regard to other Device or Strongly-ordered accesses.

Figure 9 shows the architectural NVIC access behavior.

Figure 9. Architectural NVIC access behavior

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In existing Cortex-M processor implementations, each SCS access has DSB instruction behavior with regard to other Device or Strongly-ordered accesses.

Figure 10 shows the implemented NVIC access behavior.

Figure 10. Implemented NVIC access behavior

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For existing Cortex-M processors, due to the pipelined nature of the processor, if an interrupt was already in the pending state, the processor can execute up to two extra instructions after enabling the interrupt in the NVIC before executing the interrupt service routine.

Figure 11 shows that after a pended interrupt is enabled, the Cortex-M processors might execute additional instructions before entering the exception handler.

Figure 11. Implemented interrupt enabling delay in Cortex-M processors

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Architectural requirements

ARM recommends that the architectural requirements are adopted.

Depending on the requirements in your application:

  • memory barriers are not required for normal NVIC programming

  • memory barriers are not required between NVIC programming and peripheral programming

  • if a pended interrupt request needs to be recognized immediately after being enabled in the NVIC, add a DSB instruction and then an ISB instruction.

If the instruction after the interrupt depends on the result of the pended interrupt, then you should add memory barrier instructions.

Example 4 shows code for handling an interrupt.

Example 4. Interrupt handling code

LDR R0, =0xE000E100 ; NVIC_SETENA address
MOVS R1, #0x1
STR R1, [R0] ; Enable IRQ #0
DSB ; Ensure write is completed
; (architecturally required, but not strictly
; required for existing Cortex-M processors)
ISB ; Ensure IRQ #0 is executed
CMP R8, #1 ; Value of R8 dependent on the execution
; result of IRQ #0 handler

If the memory barrier instructions are omitted, then the CMP instruction is executed before the interrupt has taken place.

Figure 12 shows how a program error might be introduced if the program expects the interrupt to take place immediately.

Figure 12. Program error due to the interrupt not taking place immediately

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To prevent a program error, application code that relies on immediate recognition of the interrupt must have the memory barrier instructions added.

Implementation requirements

Depending on the requirements in your application:

  • memory barriers are not required for normal NVIC programming

  • if a pended interrupt request must be recognized immediately after being enabled in the NVIC, add an ISB instruction.

Note

Since a NVIC access already has DSB instruction behavior, omitting the DSB instruction still permits an enabled and pended interrupt to be recognized immediately.

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