3.6. System implementation requirements

As well as memory ordering at the processor level, system level design can also affect memory ordering and might require extra steps to ensure correctness of the program operations.

Write buffers

Write buffers might be present within the processor, or can be present in bus components, such as AHB to APB bridges, or memory interfaces. The advantage of a write buffer is that it can enhance system performance. By using a write buffer, during a memory write, subsequent instructions can be executed without waiting for the write operation to be completed.

Figure 5 shows locations where write buffers might be used and their effect.

Figure 5. Locations where write buffers might be used and their effect

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When a write buffer is present, it is possible to start another data transfer while the first one is still taking place. This might result in an error if the subsequent operations on the processor rely on the completion of the buffered write. In typical memory or peripheral accesses on the Cortex-M processors this is not a problem, because data can only be accessed with one bus path and no bus transaction reordering can take place within the bus system. But if the interaction between the two memory operations can be dependent in other ways, additional measures might be needed to ensure correct ordering of the operations.

The memory barrier instructions, DMB and DSB, can be used to ensure that the write buffer on the processor has completed its operation before subsequent operations can be started. However, it does not check the status of the bus level write buffers. In such cases, if the system is based on AHB or AHB Lite, you might need to perform a dummy read through the bus bridge to ensure that the bus bridge has completed its operation. Alternatively, a SoC design might have a device specific status register to indicate whether the bus system write buffer is idle.

Note

The Cortex-M0 processor (r0p0) and the Cortex-M0+ processor (r0p0) do not include a write buffer in their processor bus interface.

System level cache

The Cortex-M0, Cortex-M0+, Cortex-M1, Cortex-M3, and Cortex-M4 processors do not have any internal cache memory. However, it is possible for a SoC design to integrate a system level cache.

Note

A small caching component is present in the Cortex-M3 and Cortex-M4 processors to accelerate flash memory accesses during instruction fetches.

In a single processor system, the existence of a data cache is unlikely to cause a memory ordering issue, however, it might have implications for power saving modes. If there are multiple bus masters in the system, and if a data set is shared, then cache memory control and memory barriers will be required to ensure correct memory ordering is maintained. This is because a cache unit can re-order the update sequence of memory.

Figure 6 shows the reordering of a memory update sequence due to a cache component.

Figure 6. Reordering of a memory update sequence due to a cache component

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Note

If multiple cache units are present, you will also require cache coherency support. Alternatively, data that is shared can be located in non-cacheable memory regions.

Hardware latency

Software errors or race conditions can also be caused by latency in hardware designs. Examples of hardware latency are the delay:

  • between triggering interrupt generation at a peripheral by a memory access, to the time the processor actually received the interrupt

  • between enabling the clock to a peripheral, to the time the peripheral can be safely accessed

  • after switching memory map by writing to a system memory control register, to the time that the new memory map arrangement becomes valid.

Note

These cannot be resolved using memory barrier instructions and should be addressed during device specification.

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