4.6. Disabling Interrupts using NVIC

In common application scenarios there is no need to use memory barriers. For example:

NVIC_EnableIRQ(device_IRQn); // Disable interrupt

Due to the processor pipeline, the Cortex-M processors can be entering the interrupt sequence at the same time as writing to the NVIC to disable the interrupt. Therefore, it is possible that an interrupt handler might be executed immediately after it is disabled at the NVIC.

Figure 13 shows the implemented interrupt disabling delay in Cortex-M processors.

Figure 13. Implemented interrupt disabling delay in Cortex-M processors

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Architectural requirement

ARM recommends that the architectural requirement is adopted.

Depending on the requirements in your application:

  • memory barriers are not required for normal NVIC programming when disabling an IRQ

  • memory barriers are not required between NVIC programming and peripheral programming

  • if it is necessary to ensure an interrupt will not be triggered after disabling it in the NVIC, add a DSB instruction and then an ISB instruction.

Example 5 shows example code for changing an interrupt vector.

Example 5. Changing an interrupt vector

#define MEMORY_PTR(addr) (*((volatile unsigned long *)(addr)))
NVIC_DisableIRQ(device_IRQn); // Disable interrupt
__DSB();
__ISB();
MEMORY_PTR(SCB->VTOR+0x40+(device_IRQn<<2))=
(void) device_Handler; // Change vector to a different one

Implementation requirements

Depending on the requirements in your application:

  • memory barriers are not required for normal NVIC programming when disabling an IRQ

  • memory barriers are not required between NVIC programming and peripheral programming

  • if it is necessary to ensure an interrupt will not be triggered after disabling it in the NVIC, add an ISB instruction.

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