AN387 - ARM Cortex-M0 DesignStart FPGA Prototyping Kit

Application Note 387



Release Information

The following changes have been made to this SMM.

                                                                                                                                                                                                                                       Change History

Date

Issue

Confidentiality

Change

12 December 2013

A

Non-Confidential

First release

13 November 2014

B

Non-Confidential

Corrected MCC switch register address

24 August 2015

C

Non-Confidential

Updated to support partial reconfiguration
Added timing closure information
Corrected filename errors
Corrected phrase to DesignStart throughout.

 

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LES-PRE-20349


 

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This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this document to.

Product Status

The information in this document is Final, which is for a developed product.

Web Address

http://www.arm.com


 

1   Preface

About this book

This book is for the Cortex-M0 DesignStart FPGA Prototyping Kit.

Implementation obligations

This book is designed to help you implement an ARM product. The extent to which the deliverables can be modified or disclosed is governed by the contract between ARM and the Licensee. There might be validation requirements which, if applicable, are detailed in the contract between ARM and the Licensee and which, if present, must be complied with prior to the distribution of any devices incorporating the technology described in this document.

Reproduction of this document is only permitted in accordance with the licenses granted to the Licensee.

ARM assumes no liability for your overall system design and performance. Verification procedures defined by ARM are only intended to verify the correct implementation of the technology licensed by ARM, and are not intended to test the functionality or performance of the overall system. You, or the Licensee, are responsible for performing system level tests.

You are responsible for applications that are used in conjunction with the ARM technology described in this document, and to minimize risks, adequate design and operating safeguards must be provided for by you. Publishing information by ARM in this book of information regarding third party products or services is not an express or implied approval or endorsement of the use thereof.

 

Product revision status

The rnpn identifier indicates the revision status of the product described in this book, where:

rn                     Identifies the major revision of the product.

pn                     Identifies the minor revision or modification status of the product.

 

Intended audience

This book is written for hardware engineers, software engineers, system integrators, and system designers, who might not have previous experience of ARM products, but want to run a complete example of a working system.

 

Using this book

This book is organized into the following chapters:

Chapter 1 Introduction

Read this chapter for an introduction to the Cortex-M0 DesignStart FPGA Prototyping Kit and its features.

Chapter 2 Overview

Read this chapter for a description of the design and layout of the FPGA and its peripherals

Chapter 3 Clocks

Read this chapter for a description of the FPGA clocks.

Chapter 4 Interrupt Assignments

Read this chapter for a description of the Cortex-M0 interrupts.

Chapter 5 Serial Communications Controller

Read this chapter for a description of the SCC operation

Chapter 6  FPGA Build Flow

Read this chapter for a description of how to run synthesis and build the FPGA.

Conventions and Feedback

The following describes the typographical conventions and how to give feedback:

Typographical conventions

The following typographical conventions are used:

monospace      denotes text that you can enter at the keyboard, such as commands, file and program names, and source code.

monospace      denotes a permitted abbreviation for a command or option. You can enter the underlined text instead of the full command or option name.

monospace italic
denotes arguments to commands and functions where the argument is to be replaced by a specific value.

monospace bold
denotes language keywords when used outside example code.

italic               highlights important notes, introduces special terminology, denotes internal cross-references, and citations.

bold                highlights interface elements, such as menu names. Denotes signal names. Also used for emphasis in descriptive lists, where appropriate.

Feedback on this product

If you have any comments and suggestions about this product, contact your supplier and give:

·      Your name and company.

·      The serial number of the product.

·      Details of the release you are using.

·      Details of the platform you are using, such as the hardware platform, operating system type and version.

·      A small standalone sample of code that reproduces the problem.

·      A clear explanation of what you expected to happen, and what actually happened.

·      The commands you used, including any command-line options.

·      Sample output illustrating the problem.

·      The version string of the tools, including the version number and build numbers.

Feedback on documentation

If you have comments on the documentation, e-mail errata@arm.com. Give:

·      The title.

·      The number, DAI0387C.

·      If viewing online, the topic names to which your comments apply.

·      If viewing a PDF version of a document, the page numbers to which your comments apply.

·      A concise explanation of your comments.

ARM also welcomes general suggestions for additions and improvements.

ARM periodically provides updates and corrections to its documentation on the ARM Information Center, together with knowledge articles and Frequently Asked Questions (FAQs).

Additional reading

This section lists publications by ARM and third parties. 

See Infocentre http://infocenter.arm.com for access to ARM documentation

Glossary

The ARM Glossary is a list of terms used in ARM documentation, together with definitions for those terms. The ARM Glossary does not contain terms that are industry standard unless the ARM meaning differs from the generally accepted meaning.

See ARM Glossary.

References

·      ARM®v7-M Architecture Reference Manual ARMv7-A and ARMv7-R edition (ARM DDI 0403D)

·      ARM® Versatile™ Express Cortex®-M Prototyping System (V2M-MPS2)Technical Reference Manual

·      ARM® Cortex®-M System Design Kit

·      ARM® Cortex®-M System Design Kit Technical Reference Manual

·      ARM® PrimeCell Synchronous Serial Port (PL022) Technical Reference Manual

·      Keil® MCBSTM32C Evaluation Board Display Board Schematic

Terms and abbreviations

 

Volatile (storage class qualifier)
In C and C++ this is the volatile storage class qualifier. In other languages the syntax and semantics might vary slightly if the concept is supported at all. The intent is to cover all storage locations that might be used for inter-processor communication variables that can be used for lock-free programming.

CMSDK                     Cortex®-M System Design Kit.

SMM                           Soft Macro Model.  An SMM is an FPGA implementation of an ARM processor, which is built with ARM development tools

ZBT                            Zero Bus Turnaround.  A ZBT RAM is an implementation of a DDR RAM, which supports back to back read and write cycles, or zero turnaround.

PSRAM                      Pseudo-SRAM.  An implementation of a DDR RAM, which has an SRAM interface, with all refresh and similar operations kept internal to the device.

 

 



2   Introduction

This chapter introduces the Cortex-M0 DesignStart prototyping kit.  It explains the other kits available and any prerequisites that are required to build the kit.

This chapter includes the following topics:

·      Cortex-M0 DesignStart Kit on page 2-1.

·      Decryption key on page 2-1.

·      Prerequisites on page 2-1.

2.1           Cortex-M0 DesignStart Kit

The Cortex-M0 DesignStart FPGA prototyping kit is part of the complete Cortex-M0 DesignStart kit.  The other key component is the Cortex-M0 DesignStart Design Kit.  This kit consists of obfuscated code for the Cortex-M0 from DesignStart processor core, which combined with a CMSDK system is available as a simulation test bench.

The Cortex-M System Design Kit (CMSDK) is a product to help silicon and FPGA designers to create Cortex-M-based systems.  It contains ready-to-use example systems for Cortex-M processors and a range of AMBA® bus fabric components for Cortex-M system development.

The Cortex-M0 DesignStart Design Kit allows you to design and compile RTL and software elements, which can then be simulated.  When these elements have been simulated, you can port them across to the Cortex-M0 DesignStart FPGA prototyping kit, which allows you to exercise these elements in a hardware environment.  Combining the two kits allows for rapid development and verification of new features and functionality.

When you are ready to access the RTL for the design and simulation phase, you should register on designstart.arm.com. After your registration is approved, download the package ARM Cortex-M0 DesignStart Design Kit.

This document describes the usage and operation of the Cortex-M0 DesignStart FPGA prototyping kit. For details regarding the Cortex-M0 DesignStart Design Kit see the relevant document that is specified in Section 0 References.

2.2           Decryption key

 

ARM supplies the V2M-MPS2 motherboard with a decryption key programmed into the FPGA.      This key is required to enable loading of the prebuilt images, which are encrypted.

Note

A battery supplies power to the key storage area of the FPGA.  Any keys stored in the FPGA are lost when battery power is lost.  If battery power is lost, you must return the board to ARM for reprogramming of the key.

2.3           Prerequisites

Rebuilding the FPGA requires the Altera Quartus Prime Standard Edition tool and a license to enable the Partial Reconfiguration feature. This license can be obtained directly from ARM.  See Section 7.3 Quartus Requirementsfor details.



3   Overview

The Soft Macro Model (SMM) is based on the Cortex-M System Design Kit (CMSDK). Extra peripherals required by the FPGA are placed in unused memory spaces.  This results in the FPGA SMM reusing most of the RTL and software in CMSDK .

 

Version

Descriptions

 

BP210

Cortex-M System Design Kit

Full version of the design kit supporting Cortex-M0, Cortex-M0 DesignStart®, Cortex-M0+, Cortex-M3 and Cortex-M4. Also contains the AHB Bus Matrix and advanced AHB components.

 

 

Image

Figure 31 : System Design Kit Diagram

 

The following topics describe the components that are connected to this SMM.

·   Memory map on page 3-4.

·   Block RAM for Booting up on page 3-6.

·   External ZBT Synchronous SRAM (SSRAM1) on page 3-6.

·   External ZBT Synchronous SRAM (SSRAM2 & SSRAM3) on page 3-6.

·   External PSRAM on page 3-6.

·   CMSDK APB subsystem on page 3-7.

·   AHB GPIO on page 3-7.

·   SPI (Serial Peripheral Interface) on page 3-7.

·   Color LCD parallel interface on page 3-7.

·   Ethernet on page 3-8.

·   VGA on page 3-8.

·   Audio I2S on page 3-8.

·   Audio Configuration on page 3-10.

·   FPGA system control and I/O on page 3-10.


 

3.1           System Overview

 

Figure 3‑2 shows the block diagram of the FPGA, indicating the Cortex-M0 processor from DesignStart, the CMSDK system, and the interfaces to the V2M-MPS2 board peripherals.

Note: This block diagram shows the functional hierarchy of the FPGA.  The physical hierarchy differs from the functional hierarchy  to support partial reconfiguration.  The physical hierarchy is shown in Figure 7‑1 : FPGA partitions.

Image

Figure 32 System Overview


 

3.2           Memory map

The following table shows the memory map:

Start Address

End Address

Description

Comment

0x41100000

0x4110FFFF

VGA Image (512x128) (AHB)

Not available in CMSDK

0x41000000

0x4100FFFF

VGA Console (AHB)

Not available in CMSDK

0x40200000

0x402FFFFF

Ethernet (Through ahb_to_extmem16. Offset 0x0 to 0x0FE for CSRs, 0x100 to 0x1FE for FIFO)

Not available in CMSDK

0x40030000

0x401FFFFF

RESERVED

-

0x4002F000

0x4002FFFF

SCC register (see SCC section)

Not available in CMSDK

0x40029000

0x4002EFFF

RESERVED

-

0x40028000

0x40028FFF

FPGA System Control & I/O, APB

Not available in CMSDK

0x40025000

0x40027FFF

RESERVED

-

0x40024000

0x40024FFF

Audio I2S, APB

Not available in CMSDK

0x40023000

0x40023FFF

SBCon (Audio Configuration), APB

Not available in CMSDK

0x40022000

0x40022FFF

SBCon (Touch for LCD module), APB

Not available in CMSDK

0x40021000

0x40021FFF

PL022 (SPI for LCD module), APB

Not available in CMSDK

0x40020000

0x40020FFF

PL022 (SPI), APB

Not available in CMSDK

0x4001F000

0x4001FFFF

CMSDK system controller

CMSDK system controller

0x40012000

0x4001EFFF

Reserved for extra GPIO / other AHB peripherals

Unused

0x40011000

0x40011FFF

CMSDK AHB GPIO #1

Identical to CMSDK

0x40010000

0x40010FFF

CMSDK AHB GPIO #0

Identical to CMSDK

0x40000000

0x4000FFFF

CMSDK APB subsystem

Identical to CMSDK

0x21000000

0x21FFFFFF

PSRAM (16MB)

Not available in CMSDK

0x20800000

0x20FFFFFF

RESERVED

-

0x20000000

0x207FFFFF

ZBTSRAM 2 & 3 (2x 32-bit). Reserved 8MB, 4MB available. The two SRAM blocks are interleaved.

Only 64KB SRAM in CMSDK

0x01010000

0x1FFFFFFF

RESERVED

-

0x01000000

0x0100FFFF

Block RAM (boot time) – reserved 64KB, 16K implemented. Memory wrapped through region.

-

0x00800000

0x00FFFFFF

RESERVED

-

0x00400000

0x007FFFFF

ZBTSRAM 1 (64-bit). Wrapped (only 4MB ZBTSRAM fitted)

Unused in CMSDK.

0x00004000

0x003FFFFF

ZBTSRAM 1 (64-bit)

Flash memory in CMSDK example system is 64KB. This is increased to 4MB in this SMM.

0x00000000

0x00003FFF

CODE region.
When zbt_boot_ctrl = 0, ZBTSRAM 1 is mapped to this region, otherwise, Remap_ctrl = 0 maps Block RAM and Remap_ctrl = 1 maps ZBTSRAM 1.

Block RAM or ZBTSRAM remap Note 1

 

Table 31 – Detailed system memory map

Note 1 The microcontroller on the V2M-MPS2 board controls the zbt_boot_ctrl signal. The zbt_boot_ctrl signal overrides the boot option to enable the ZBT RAM to be used.

Many parts of the memory map have the same programmer’s view as CMSDK.


 

3.3           Block RAM for Booting up

The SMM implements 16KB of FPGA internal block RAM as 32-bit AHB SRAM with a boot-code to enable the system to start in a defined state. You can then add extra functions.

By default, the microcontroller using a zbt_boot_ctrl signal overrides the boot option.

3.4           External ZBT Synchronous SRAM (SSRAM1)

This section describes the Zero Bus Turnaround (ZBT) SRAM in the CODE region.

This interface consists of two external 32-bit ZBT SSRAMs in parallel, forming a 64-bit ZBT SSRAM. 8MB of memory space is allocated, but only 4MB is available (each ZBT SSRAM is 2MB).

By default, the first 64KB is aliased to the FPGA internal block RAM. You can turn off the aliasing by clearing the REMAP register in the CMSDK system controller.

CMSDK_SYSCON->REMAP = 0;

By default, the SMM design overwrites this alias with an extra boot control so that it boots from ZBT SRAM.

You can also turn off the default ZBT SRAM boot control by changing the TOTALSYSCONS variable in the board.txt file to 0.

TOTALSYSCONS: 1  -> TOTALSYSCONS: 0

This memory space connects through AHB.

3.5           External ZBT Synchronous SRAM (SSRAM2 & SSRAM3)

The ZBT SSRAM in SRAM region is set up as two external ZBT SSRAMs, connected to two independent ZBT interfaces. In the 8MB memory region, 4MB of ZBT are available.

The address of the ZBT SSRAM is interleaved as shown in the following table.

Upper 32-bit ZBT SSRAM3

Lower 32-bit ZBT SSRAM2

0x207FFFFC (wrap round to 0x203FFFFC)

0x207FFFF8 (wrap round to 0x203FFFF8)

0x20400004 (wrap round to 0x20000004)

0x20200000 (wrap round to 0x20000000)

0x203FFFFC

0x203FFFF8

0x2000000C

0x20000008

0x20000004

0x20000000

Table 32 – 32-bit ZBT Memory Map

This memory space connects through AHB.

 

3.6           External PSRAM

A 16MB 16-bit PSRAM area is available and the memory map allocates the address-range 0x21000000 -0x21FFFFFF. This PSRAM space enables large test programs to be used in the SRAM region of the Cortex-M memory space.

Note: Running code from SRAM region is slower than from CODE region because the internal bus structure is not optimized for running programs from this region.

3.7           CMSDK APB subsystem

The SMM uses APB subsystem in CMSDK.

Address

Item

Notes

0x4000F000-0x4000FFFF

APB expansion port 15

Not used. Reserved for micro DMA controller configuration port

0x4000E000-0x4000EFFF

APB expansion port 14

Not used

0x4000D000-0x4000DFFF

APB expansion port 13

Not used

0x4000C000-0x4000CFFF

APB expansion port 12

Not used

0x4000B000-0x4000BFFF

APB test slave

For validation of AHB to APB bridge

0x40009000-0x4000AFFF

Ports on APB slave multiplexer

Not used

0x40008000-0x40008FFF

Watchdog

 -

0x40007000-0x40007FFF

Ports on APB slave multiplexer

Not used

0x40006000-0x40006FFF

UART2

-

0x40005000-0x40005FFF

UART1

Not used

0x40004000-0x40004FFF

UART0

 -

0x40003000-0x40003FFF

Ports on APB slave multiplexer

Not used

0x40002000-0x40002FFF

Dual timer

 -

0x40001000-0x40001FFF

Timer1

 -

0x40000000-0x40000FFF

Timer0

 -

Table 33 – APB Memory Map

3.8           AHB GPIO

The SMM uses CMSDK AHB GPIO #0 and #1. See the CMSDK TRM.

3.9           SPI (Serial Peripheral Interface)

The SMM implements two PL022 SPI modules:

·      General-purpose SPI module that connects to the general-purpose SPI connector, J21.

·      Color LCD module control.

3.10        Color LCD parallel interface

The color LCD module has two interfaces:

·      SPI for LCD module that is used for sending image data to the LCD.

·      I2C to transfer data input from the touch screen.

These interfaces are connected to a STMicroelectronics STMPE811QTR Port Expander with Advanced Touch Screen Controller on the KEIL MCBSTM32C display board.  This display board contains an Ampire AM-240320LG 2.4” Touch Panel.  Schematics for this board are listed in the reference section.

Self-test that is provided with the MPS2 includes example code for both of these interfaces.

3.11        Ethernet

The SMM design connects SMSC LAN9220 through AHB to external memory block.

The SMM self-test code includes example code for a simple loopback operation.

3.12        VGA

Table 3‑4 shows the memory map for controlling a screen using the VGA interface

Address

Description

0x41000000 - 0x4100FFFF

Writes to the current location of the cursor.

0x41100000 - 0x4110FFFF

512x128 image area at the top right of the screen. 0x41100000 is the top left of the area and 0x4110FFFF is the bottom right. HADDR[16:2] = YYYYYYYXXXXXXXX where X and Y are the horizontal and vertical pixel offset respectively.

 

Table 34 – VGA Memory Map

For the image data, each pixel requires one 32-bit word, therefore, a total of 256KB are needed. The values in the data buffer are packed as 4 bits per-channel in the format 0x00000RGB.  

The pixel in the top left-hand corner of the display occupies address 0x41100000 with each successive row using an offset of 0x00000400 from the previous row. For example: the left-most pixel (LMP) of the second row is at 0x41100400 and the LMP of the third row is at 0x41100800.

3.13        Audio I2S

A simple FIFO interface generates and receives I2S audio.

Address

Name

Information

0x40024000

CONTROL

Control Register

[31:18]: Reserved

[17]: Audio codec reset control (output pin)

[16]: FIFO reset

[15]: Reserved

[14:12]: RX Buffer IRQ Water Level - Default 2

 (IRQ triggers when more less two word space available)

[11]: Reserved

[10: 8]: TX Buffer IRQ Water Level - Default 2

  (IRQ triggers when more than two word space available)

[7: 4]: Reserved

[3]: RX Interrupt Enable

[2]: RX Enable

[1]: TX Interrupt Enable

[0]: TX Enable

0x40024004

STATUS

Status register

[31:6]: Reserved

[5]: RX Buffer Full

[4]: RX Buffer Empty

[3]: TX Buffer Full

[2]: TX Buffer Empty

[1]: RX Buffer Alert (Depends on Water level)

[0]: TX Buffer Alert (Depends on Water level)

0x40024008

ERROR

Error status register

[31:2]: Reserved

[1]: RX overrun - write 1 to clear

[0]: TX overrun or underrun - write 1 to clear

0x4002400C

DIVIDE

Divide ratio register (for Left or Right clock)

[31:10]: Reserved

[9:0] LRDIV (Left/Right) Default = 0x80

     12.288MHz / 48KHz / 2 (L+R) = 128

0x40024010

TXBUF

Transmit Buffer FIFO Data Register (WO)

[31:16]: Left Channel

[15:0]: Right Channel

0x40024014

RXBUF

Receive Buffer FIFO Data Register (RO)

[31:16] Left Channel

[15: 0] Right Channel

0x40024018 –

0x400242FC

RESERVED

-

0x40024300

ITCR

Integration Test Control Register

[31:1]: Reserved

[0]: ITCR

0x40024304

ITIP1

Integration Test Input Register 1

[31:1]: Reserved

[0]: SDIN

0x40024308

ITOP1

Integration Test Output Register 1

[31:4]: Reserved

[3]: IRQOUT

[2]: LRCK

[1]: SCLK

[0]: SDOUT

Table 35 - Audio I2S Memory Map

3.14        Audio Configuration

The SMM implements a simple SBCon interface that is based on I2C.

 

3.15        FPGA system control and I/O

The SMM implements an FPGA system control block.

Address

Name

Information

0x40028000

FPGAIO->LED0

LED connections

[31:2]: Reserved

[1:0]: LED

0x40028004

RESERVED

 

0x40028008

FPGAIO->BUTTON

Buttons

[31:2]: Reserved

[1:0]: Buttons

0x4002800C

RESERVED

 

0x40028010

FPGAIO->CLK1HZ

1Hz up counter

0x40028014

FPGAIO->CLK100HZ

100Hz up counter

0x40028018

FPGAIO->COUNTER

Cycle Up Counter

Increments when 32-bit prescale counter reach zero.

0x4002801C

FPGAIO->PRESCALE

Bit[31:0] – reload value for prescale counter.

0x40028020

FPGAIO->PSCNTR

32-bit prescale counter – current value of the pre-scaler counter. The Cycle Up Counter increment when the prescale down counter reach 0. The pre-scaler counter is reloaded with PRESCALE after reaching 0.

0x40028024

RESERVED

 

0x4002804C

FPGAIO->MISC

Misc. control

[31:7]: Reserved

[6]: CLCD_BL_CTRL

[5]: CLCD_RD

[4]: CLCD_RS

[3]: CLCD_RESET

[2]: RESERVED

[1]: SPI_nSS

[0]: CLCD_CS

Table 36 – System Control and I/O Memory Map



4   Clocks

The following table shows the Source Clocks for the system.

 

Name

Frequency

OSCCLK[0]

50MHz

OSCCLK[1]

24.576MHz

OSCCLK[2]

25MHz

CFGCLK

0.5MHz

CS_TCK

Determined by debugger

SPICFGCLK

7.5MHz

Table 41 : Source Clocks

The following table shows the Derived Clocks for the system.

Name

Frequency

Division

Factor

Multiplication Factor

Derived From

SYSCLK

25MHz

2

0

OSCCLK[0]

DBGCLK

25MHz

2

0

OSCCLK[0]

SPICLCD

25MHz

2

0

OSCCLK[0]

SPICON

25MHz

2

0

OSCCLK[0]

I2CCLCD

25MHz

2

0

OSCCLK[0]

I2CAUD

25MHz

2

0

OSCCLK[0]

AUDMCLK

12.29MHz

2

0

OSCCLK[1]

AUDSCLK

3.07MHz

8

0

OSCCLK[1]

 Table 42 : Derived Clocks

 



5   Interrupt assignments

The SMM uses the following interrupt assignments. These interrupt assignments are different from the default CMSDK assignments:

 

Number

Interrupt source

Related to CMSDK

NMI

Watchdog

 

0

UART 0 receive interrupt

 

1

UART 0 transmit interrupt

 

2

UART 1 receive interrupt (Reserved)

 

3

UART 1 transmit interrupt (Reserved)

 

4

UART 2 receive interrupt

 

5

UART 2 transmit interrupt

 

6

GPIO 0 combined interrupt

 

7

GPIO 1 combined interrupt

 

8

Timer 0

 

9

Timer 1

 

10

Dual Timer

 

11

SPI #0 and SPI #1

 

12

UART overflow (0, 1 & 2)

UART 0 overflow

13

Ethernet

UART 1 overflow

14

Audio I2S

UART 2 overflow

15

Touch Screen

 

Table 51 : Interrupts



6   Serial Communication Controller (SCC)

The SMM implements communication between the microcontroller and the FPGA system through an SCC interface.

 

Image

Figure 61 : Diagram of the SCC Interface

 

The read-addresses and write-addresses of the SCC interface do not use bits [1:0].

All address words are word-aligned.

  

Address

Name

Information

0x000

CFG_REG0

[31:1]        Reserved

[0]             1 = REMAP Block RAM to ZBT

0x004

CFG_REG1

[31:8]        Reserved

[7:0]          MCC LEDs:  0 = OFF, 1 = ON 

0x008

CFG_REG2

Reserved 

0x00C

CFG_REG3

[31:8]        Reserved

[7:0]          MCC switches:  0 = OFF, 1 = ON

0x010

CFG_REG4

[31:4]        Reserved

[3:0]          Board Revision

0x014

CFG_REG5

Reserved

0x018

CFG_REG6

Reserved

0x01C

CFG_REG7

Reserved

0x020 – 0x09C

RESERVED

-

0x0A0

SYS_CFGDATA_RTN

32-bit DATA [r/w]

0x0A4

SYS_CFGDATA_OUT

32-bit DATA [r/w]

0x0A8

SYS_CFGCTRL

[31]:         Start (generates interrupt on write to this bit)

[30]:         R/W access

[29:26]:    Reserved

[25:20]:    Function value

[19:12]:    Reserved

[11:0]:      Device (value of 0/1/2 for supported clocks)

0x0AC

SYS_CFGSTAT

Bit 0:        Complete

Bit 1:        Error

0x0AD – 0x0FC

RESERVED

-

0x100

SCC_DLL

DLL lock register

[31:24]     DLL LOCK MASK[7:0] - These bits indicate that the DLL lock is masked.

[23:16]     DLL LOCK MASK[7:0] - These bits indicate whether the DLLs are locked or unlocked.

[15:1]:      Reserved

[0]            This bit indicates whether all enabled DLLs are locked:

0x104 – 0xFF4

RESERVED

 -

0xFF8

SCC_AID

SCC AID register is read only

[31:24]:    FPGA build number

[23:20]:    V2M-MPS2 target board revision    (A = 0, B = 1)

[19:8]       Reserved

[7:0]         number of SCC configuration registers

 

0xFFC

SCC_ID

SCC ID register is read only

[31:24]:    Implementer ID: 0x41 = ARM

[23:20]:    Application note IP variant number (note 1)

[19:16]:    IP Architecture: 0x4 =AHB

[11:4]:      Primary part number: 387 = AN387  

[3:0]:        Application note IP revision number (note 1)

Table 61 – SCC Register memory map

Note 1 The variant and revision numbers relate to the rXpY number. For example, for r1p0 processors the 1 would be the variant number and the 0 would be the revision number.



7   FPGA Build Guide

This section describes the steps that are required to build an FPGA bitfile from the supplied source code.

Note:

To build the FPGA files, Altera Quartus Prime Standard Edition is required, not Quartus Prime Lite.  A license to enable the Partial Reconfiguration feature is also required.  See Section 7.3 Quartus Requirements for additional information.

7.1           FPGA Project Structure

Before compiling a new bitfile for the Cortex-M0 DesignStart FPGA, it is necessary to understand the layout of the FPGA project.

The FPGA project takes advantage of the Altera partial reconfiguration flow.  This flow allows a base image to be built and downloaded to an FPGA, and then a subsystem, as a partial reconfiguration block, which is downloaded over a portion of the base image.

Included with the MPS development board is an encrypted base image that includes the Cortex-M0 processor from DesignStart core, and the CMSDK subsystem, as Figure 3-2 System Overview shows.

Within the FPGA, this system is divided into three distinct blocks, or partitions; as shown in Figure 7‑1 : FPGA partitions.

Image

Figure 71 : FPGA partitions

These three partitions are:

1)   Base Partition. This consists of the IO pins, PLLs, and clock routing.

2)   Core Partition. This consists of the Cortex-M0 DesignStart core

3)   User Partition.  This consists of the CMSDK and FPGA APB subsystems, plus various peripherals for interfacing to the installed memory and other external interfaces.

Only the User Partition can be modified.  The functionalities of the Base Partition and Core Partition are provided by the supplied encrypted base image.

The Altera Quartus project allows you to modify the User Partition. Download this as a partial reconfiguration block, overwriting the original supplied User Partition.

7.1.1        Code Restrictions

To compile the Quartus project, it is necessary to have the source code for the Base Partition.  The source code is provided as part of the Cortex-M0 DesignStart FPGA prototyping kit.

Note:  You must not modify any files that form the Base Partition.  Modifying these files results in unpredictable behavior. If the files are inadvertently altered, the original versions must be re-installed from the Cortex-M0 DesignStart FPGA prototyping kit.

7.2           FPGA Source Files

The following folders and their contents are required to create a bitfile that enables the Cortex-M0 processor from DesignStart to be run on the MPS2 development board. These files are included as part of the Cortex-M0 DesignStart FPGA prototyping kit.

·     resources folder, includes the cmsdk_r1p0 and smm_common folders.

·     RevB or RevC folder, depending on the version of MPS2 board is to be used, RevB for MPS2 board, RevC for MPS2+ version.

·     docs folder, includes this document.

All these folders can also be found in the DVD that accompanies the MPS2 Rapid Prototyping system board, in the app_notes/AN387/design_start folder.

The FPGA source files must be assembled in a single directory. ARM recommends the following directory structure.

Image

Figure 72 : Recommended Folder Structure

When all these files have been assembled as indicated, the following steps enable you to modify the Cortex-M0 DesignStart on the MPS2 development board.

7.3           Quartus Requirements

7.3.1        Quartus Version

The Cortex-M0 DesignStart FPGA project must use Altera Quartus Prime Standard edition, version 15.1 or later.  The Cortex-M0 DesignStart FPGA prototyping kit makes use of the Partial Reconfiguration feature of Quartus, which is only available to be licensed with the standard edition.  Quartus Prime Lite is not suitable.

7.3.2        Quartus License

To enable the Partial Reconfiguration feature, an additional license is required to the basic Quartus Prime Standard Edition license.  If you do not have the Partial Reconfiguration feature enabled in your existing license then download ARM_PR_license_request_form which contains instructions for how ARM can then issue a partial reconfiguration license to you.

7.4           Build Flow

The following instructions describe how to create a new User Partition bitfile and how to download this to the MPS2 board.

1.    Open Altera Quartus Prime.

2.    Select File -> Open Project. Navigate to the RevX/SMM_M0DS/synthesis folder where X is the board revision. Select and open the Quartus project for the M0 DesignStart file titled SMM_M0DS_AN387.qpf. The design is ready for compilation and synthesis.

3.    To compile the design, select Processing -> Start Compilation. This compiles the standard design and creates various report files in the output_files folder. After compilation is complete, an SOF file, titled user.sof, is created in the output_files folder.

Note: The supplied Quartus project is a partial reconfiguration project with a Base and User Revisions.  These revisions can be seen in the revisions tab of the project navigator window.  Do not attempt to compile the Base Revision.  Always compile the User Revision.  If you accidentally compile the Base Revision, then delete the whole synthesis directory and re-install from Cortex-M0 DesignStart FPGA prototyping kit. The project as shipped defaults to the User Revision so selecting the Processing -> Start Compilation builds the User Revision. The Play icon on the task bar also accomplishes this. 

Timing: If the modified code fails to meet timing, see the instructions in section 7.5 regarding how to modify the fitter seed.

4.    Select Tools -> TCL Scripts, then select build_user_bitfile.tcl.  Select Run.  This script converts the SOF file into a partial reconfiguration RBF file, titled 387us_03.rbf, also in the output_files folder.

Note: To allow for a degree of traceability between different user bitfiles, the final two digits can be used as a version number.  Note also that the file system on the MPS2 board only allows for 8:3 filenames, so only two digits are possible.  To change these two digits when generating, they are contained in the header of
build_user_bitfile.tcl as the BUILD_NUM variable, and can be modified with any text editor.

5.    To download the resultant user rbf file, power the board with the supplied power supply, connect a USB lead to your computer and the USB-B port (labeled USB) on the board. The computer  recognizes a new USB device called “V2M-MPS”.

6.    Access the V2M-MPS2 device and copy the 387us_XX.rbf file to the folder  MB\HBI0263(B/C)\AN387.

7.    Change which image is programmed into the FPGA.

On the USB device, the “board.txt” file selects which hardware image is programmed into the FPGA. This affects what application note to run. The board file is located in the directory “MB\HBI0263(B/C)\board.txt”.

The image to be loaded is selected with a line starting “APPFILE:”. A selection of images has been preloaded onto the USB device. All but one has been commented out with a “;” character.

To select an image, remove the comment “;” in front of the appropriate line and ensure that all other “APPFILE:” references are preceded by the comment character.

For example, the following file selects Application Note 387 which is the Cortex-M0 DesignStart.

 

BOARD: HBI0263

TITLE: Motherboard configuration file

 

[MCCS]

MBBIOS: mbb_v217.ebf         ; MB BIOS IMAGE

 

[APPLICATION NOTE]           ; Please select the required processor

;APPFILE: AN382/an382_v2.txt ; - Cortex-M0

;APPFILE: AN383/an383_v2.txt ; - Cortex-M0+

;APPFILE: AN384/an384_v2.txt ; - Cortex-M1

;APPFILE: AN385/an385_v2.txt ; - Cortex-M3

;APPFILE: AN386/an386_v2.txt ; - Cortex-M4

;APPFILE: AN399/an399_v2.txt ; - Cortex-M7

;APPFILE: AN400/an400_v2.txt ; - Cortex-M4 with coresight

APPFILE: AN387/an387_v3.txt  ; - Cortex-M0 DesignStart

 

 

8.       Specify the bitfile to use. Modify the file “an387_v3.txt” located in the “MB\HBI0263(B/C)\AN387” folder.

Use the following line to select the bitfile to load:
        “F1FILE: 387us_03.rbf        ;FPGA1 Filename – PR user partition”

Note: The board is set to program two bitfiles, the first
387st_03.rbe is the base encrypted image which contains a full design.  If no modifications are required to the User Partition, you can set TOTALFPGAS to 1.  However, if a modified User Partition is required, set this value back to 2.

9.       When steps 7 and 8 have been completed, save and close both files.

10.    Press the Power ON button on the MPS2 board, both bitfiles load and the board is ready to use.

Note: As a check, particularly if a modified User Partition does not seem to have been downloaded, in the root directory of V2M-MPS2 check
log.txt.  This details which files were loaded at boot-up.

7.5           Timing closure

The build has the possibility of failing to meet timing because of the modification of the user code. In these circumstances it has been found that modifying the fitter seed results in an alternative placement and usually successful timing.

Follow these steps to modify the fitter seed.

1)   Select Assignments -> Settings

2)   Within the settings dialog, select Compiler Settings.

Image

 

3)   Select Advanced Settings, (Fitter).  The settings are in alphabetical order,

4)   Descend to “Fitter Initial Placement Seed” and select a revised value.

Image

 

Note: Altera Design Space Explorer offers an automatic way of sweeping fitter seeds to achieve timing closure.  However, Design Space Explorer does not operate correctly on this project because this project is a partial reconfiguration revision.

 

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