AN415 - Example LogicTile Express 20MG design for a V2M-Juno Motherboard

Application Note 415



Release Information

The following changes have been made to this Application Note.

Change History

Date

Issue

Confidentiality

Change

27/06/2014

A

Non-Confidential

First release

18/05/2015

B

Non-Confidential

Updated to r0p1 firmware release

08/07/2016

C

Non-Confidential

Added interrupt details and improved memory map.

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LES-PRE-20349


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2   Overview

2.1           Purpose of this application note

This application note discusses the operation of an example design for a LogicTile Express 20MG (V2F-1XV7) operating alongside a V2M-Juno Motherboard.  It examines the contents of the V2F-1XV7, the system interconnect, the clock structure, and specifics of the programmer’s model directly relevant to the application note operation.

Reading this application note prepares a user to debug and analyze the operation of the provided example design, make changes to the example design, connect his own AXI or AHB based masters, and AXI, AHB or APB slaves.

2.2           References

·      Release notes as supplied with the V2M-Juno motherboard.

·      ARM DDI0524 - VersatileTM  Express Juno Development Platform (V2M-Juno) Technical Reference Manual.

·      ARM 100113_0000_04_en - VersatileTM  Express Juno Development Platform (V2M-Juno) Technical Reference Manual.

·      ARM 100122_0100_00_en - VersatileTM  Express Juno r1 Development Platform (V2M-Juno r1) Technical Reference Manual.

·      ARM 100114_0200_00_en - VersatileTM  Express Juno r2 Development Platform (V2M-Juno r2) Technical Reference Manual.

2.3           Terms and abbreviations

DDR
Double Data Rate DRAM.

DMA
Direct Memory Access.

DMC
Dynamic Memory Controller.

DRAM
Dynamic Random Access Memory.

RAM
Random Access Memory.

FPGA
Field Programmable Gate Array.

AXI
Advanced eXtensible Interface.

SCC
Serial Configuration Controller.

DCC
Daughterboard Configuration Controller.

TRM
Technical Reference Manual.

DCM
Digital Clock Manager.

APB
Advanced Peripheral Bus.

RTL
Register transfer level.

XML
Extensible Markup Language.

TMIF
Thin Links Master Interface.

TSIF
Thin Links Slave Interface.

Tsu
Setup time required by input.

Th
Hold time required by input.

Tco-min
Minimum time between clock and valid output data.

Tco-max
Maximum time between clock and valid output data.

 

 

3   Getting Started

The steps below show you how to set up the hardware platform and copy the necessary configuration files to the V2M-Juno motherboard USB Flash disk and program the LogicTile Express FPGA image.

  1. Place the V2F-1XV7 daughterboard on the tile site of the V2M-Juno  motherboard.
  2. Note that the logic tile needs to be supplied with 12 volts DC through a special power cable connected between the four pin disk drive connector of the motherboard power regulator module and the six pin power input connector of the logic tile.
  3. Connect USB, UART0, and power cables, and power up the boards as described in the V2M-Juno release notes.
  4. After the host computer recognizes the motherboard Micro-SD card as a USB mass storage device, you must copy the application note boardfiles on to the card. The easiest way to copy the boardfiles on to the card is to follow the system recovery procedure given in the release notes supplied with the AN415 bundle.
  5. Power cycle the boards by pressing the black button and then the red button.  The application note bitfile is uploaded to the V2F-1XV7 FPGA.
  6. The system will now be fully configured and ready for use.

4   System architecture

This system is AXI (AMBA 4) based. The example V2F-1XV7 image exposes one AXI slave and one AXI master port via Thin Links interfaces to the V2M-Juno motherboard.

Image

Figure 41 System Architecture

Note that the direction of the arrows indicates the direction of control, that is it points from the Master to the Slave. An AXI bus contains signals going in both directions.

4.1           Module functionality

NIC-400

The NIC-400 is a high performance AMBA-compliant network infrastructure used to connect together the AXI masters and peripherals in AN415.

SBCON

The SBCON block provides an interface with which the EEPROM contained on the DDR3 SODIMM fitted to the V2F-1XV7 board can be read.

MIG-7

The MIG-7 is a DDR3 memory controller configured using Xilinx Vivado tools.

FPGA RAM

Block RAM in the FPGA provides a memory area for general use.

SCC

The SCC (Serial Configuration Controller) provides an interface between the V2F-1XV7 DCC (Daughterboard Configuration Controller) and the NIC-400. This interface is responsible for allowing the FPGA to control the V2F-1XV7 user LEDs and to see the board DIP switches.

DMA

A PL330 DMA controller is available to move data to and from the TLX400 TSIF.

TLX400 TSIF

The TLX400 is a modified NIC400 Thin Links implementation. It has been split between this application note and the Juno chip providing an efficient high bandwidth link. The TSIF is a slave interface from the point-of-view of the Juno chip and allows AN415 to master into Juno.

TLX400 TMIF

The TLX400 is a modified NIC400 Thin Links implementation. It has been split between this application note and the Juno chip providing an efficient high bandwidth link. The TMIF is a master interface from the point-of-view of the Juno chip and allows Juno to master into AN415.

4.2           Modules revision

Module                                    Revision

NIC-400 Bus Matrix             r0p2

PL330 DMA                            r1p0

SCC                                          r0p3

Mig 7 Series for rev B boards       v1.6

Mig 7 Series for rev C boards       v2.0

Table 1 Modules revision

 


4.3           Clock architecture

The design of the clock architecture, the DCMs and clock loops on the V2F-1XV7 minimize clock skew (time difference) across the system.

Section 9.1- Default, minimum and maximum operating frequencies describes which oscillator controls which internal clock, along with their minimum, maximum and default frequencies.

For information how to set up and change the frequencies of clocks OSC0-OSC5, please refer to V2M-Juno Motherboard TRM.

Image

Figure 42 – Clock Domains

There are 6 clock domains in this design.

Main

DDR, runs the MIG-7. Created internally.

SCC, created by external DCC microcontroller.

TLX Master, generated by V2M-Juno.

TLX Slave, sent to V2M-Juno.

TLX Internal, independent to master and slave clocks.

4.4           Reset architecture

The reset signal CB_nRST from the motherboard is synchronized to the correct clock domains to reset all the peripherals in the Versatile Express FPGA Daughterboard.

The reset signal nPLLRESET from the DCC controller is used to reset MMCM during power-up sequence.

The reset signal CB_nPOR is not used in the design.

5   Hardware description

5.1           V2F-1XV7  wrapper  (V2F_1XV7_wrapper)

This level defines the mapping from the V2F-1XV7 XN, XP and XS busses into their functional allocations. The wrapper also contains clock structure and ties off static pins.

5.2           AN415 top level (AN415_toplevel)

This level connects all the major Application Note components together.

The top level RTL is provided so modules can be added and removed by the user.

All modules except SCC are high value AXI blocks, and are only provided as .NGC netlists.

Two constraint files (xdc) are included for the application note, which show all FPGA pins used on the V2F-1XV7 daughterboard and timing constraints.

5.3           Thin Links demultiplexing scheme

Thin Links is implemented with a multiplexing scheme. This scheme is included in the Thin Links RTL block and is not available for user modification.

5.4           Header HDRX pin allocation

The AXI bus connects to the HDRX as shown.  Thin Links connected AXI master and slave bus connects via HDRX header to an external AXI master and slave.

5.5           Interrupt mapping

AN415 provides 4 interrupt outputs. Only the first is used by V2M-Juno.

Interrupt

AN415

V2M-Juno

SB_INT[0]

PL330 irq[0]

Connected

SB_INT[1]

Reserved

Reserved

SB_INT[2]

Reserved

Reserved

SB_INT[3]

Reserved

Reserved


 

5.6           X Bus connectivity table

Thin Links port

Xbus

 

Xbus

Thin Links port

tmif_clko

XP[110]

 

tsif_valid_o

XN[70]

tmif_clki

XP[100]

 

XP[92]

tmif_ctl_i[0]

tmif_ctl_o

XN[126]

 

XP[90]

tmif_ctl_i[1]

tmif_data_o[0]

XN[159]

 

XN[124]

tmif_data_i[0]

tmif_data_o[1]

XN[157]

 

XP[123]

tmif_data_i[1]

tmif_data_o[2]

XN[155]

 

XN[122]

tmif_data_i[2]

tmif_data_o[3]

XN[153]

 

XP[121]

tmif_data_i[3]

tmif_data_o[4]

XN[151]

 

XN[120]

tmif_data_i[4]

tmif_data_o[5]

XP[159]

 

XP[128]

tmif_data_i[5]

tmif_data_o[6]

XN[158]

 

XP[126]

tmif_data_i[6]

tmif_data_o[7]

XP[157]

 

XP[124]

tmif_data_i[7]

tmif_nrst

XP[89]

 

XN[89]

tmif_valid_i

tsif_nrst

XP[70]

 

XN[33]

tsif_ctl_i

tmif_valid_o

XP[125]

 

XN[0]

tsif_data_i[0]

tsif_clko

XP[59]

 

XN[2]

tsif_data_i[1]

tsif_clki

XP[49]

 

XN[4]

tsif_data_i[2]

tsif_ctl_o[0]

XP[67]

 

XN[6]

tsif_data_i[3]

tsif_ctl_o[1]

XP[69]

 

XN[8]

tsif_data_i[4]

tsif_data_o[0]

XN[35]

 

XP[0]

tsif_data_i[5]

tsif_data_o[1]

XP[36]

 

XN[1]

tsif_data_i[6]

tsif_data_o[2]

XN[37]

 

XP[2]

tsif_data_i[7]

tsif_data_o[3]

XP[38]

 

XN[3]

tsif_data_i[8]

tsif_data_o[4]

XN[39]

 

XP[4]

tsif_data_i[9]

tsif_data_o[5]

XP[31]

 

XN[5]

tsif_data_i[10]

tsif_data_o[6]

XP[33]

 

XP[6]

tsif_data_i[11]

tsif_data_o[7]

XP[35]

 

XN[7]

tsif_data_i[12]

tsif_data_o[8]

XP[37]

 

XP[8]

tsif_data_i[13]

tsif_data_o[9]

XP[39]

 

XN[9]

tsif_data_i[14]

tsif_data_o[10]

XN[40]

 

XP[1]

tsif_data_i[15]

tsif_data_o[11]

XN[42]

 

XP[3]

tsif_data_i[16]

tsif_data_o[12]

XN[44]

 

XP[5]

tsif_data_i[17]

tsif_data_o[13]

XN[46]

 

XP[7]

tsif_data_i[18]

tsif_data_o[14]

XN[48]

 

XP[9]

tsif_data_i[19]

tsif_data_o[15]

XP[40]

 

XN[10]

tsif_data_i[20]

tsif_data_o[16]

XN[41]

 

XN[12]

tsif_data_i[21]

tsif_data_o[17]

XP[42]

 

XN[14]

tsif_data_i[22]

tsif_data_o[18]

XN[43]

 

XN[16]

tsif_data_i[23]

tsif_data_o[19]

XP[44]

 

XP[10]

tsif_data_i[24]

tsif_data_o[20]

XN[45]

 

XN[11]

tsif_data_i[25]

tsif_data_o[21]

XP[46]

 

XP[12]

tsif_data_i[26]

tsif_data_o[22]

XN[47]

 

XN[13]

tsif_data_i[27]

tsif_data_o[23]

XP[48]

 

XP[34]

tsif_valid_i

5.7           Header HDRY pin allocation

Header Y is only used for clock and reset lines.

6   Programmer’s model

The example design for a V2F-1XV7 provides:

      SCC memory mapped registers

      FPGA SRAM

      DDR3 memory (DMC)

      DMA controller

      AXI master bus to V2F-1XV7 daughterboard slave port

      AXI slave bus from V2F-1XV7 daughterboard master port

      One spare AXI port slave, one spare AXI port master

      Two spare APB ports


 

6.1           Example AXI memory map

The AXI slave implemented by AN415 exists in the 256MB memory window from 0x00_6000_0000 to 0x00_6FFF_FFFF of  V2M-Juno.

Different AXI masters can see different memory areas. The visibility is detailed for each master with Yes indicating access is available and N/C indicating no connection. Juno refers to transfers initiated by V2M-Juno over the TLX interface. DMA refers to accesses from the PL330 DMA controller. Spare refers to accesses from the spare AXI port reserved for user expansion.

 

Memory Start

Memory End

Size

Bus

Juno

AXI-M

DMA

AXI-M

Spare

AXI-M

AN415

0x00_0000_0000

0x00_2EFF_FFFF

752MB

TLX

AXI-S

N/C

Yes

Yes

Access to V2M-Juno

0x00_2F00_0000

0x00_2FFF_FFFF

16MB

-

N/C

N/C

N/C

Reserved

0x00_3000_0000

0x00_5FFF_FFFF

768MB

TLX

AXI-S

N/C

Yes

Yes

Access to V2M-Juno

0x00_6000_0000

0x00_6000_FFFF

64 KB

-

N/C

N/C

N/C

Reserved

0x00_6001_0000

0x00_6001_FFFF

64 KB

APB

Yes

N/C

Yes

SCC

0x00_6002_0000

0x00_6002_FFFF

64 KB

APB

Yes

N/C

Yes

PL330 config

0x00_6003_0000

0x00_6003_FFFF

64 KB

APB

Yes

N/C

Yes

SBCON

0x00_6004_0000

0x00_6004_FFFF

64 KB

APB

Yes

N/C

Yes

Spare APB slave 1

0x00_6005_0000

0x00_6005_FFFF

64 KB

APB

Yes

N/C

Yes

Spare APB slave 2

0x00_6006_0000

0x00_600F_FFFF

640 KB

-

N/C

N/C

N/C

Reserved

0x00_6012_0000

0x00_601F_FFFF

896 KB

AXI

Yes

Yes

Yes

Reserved  for RAM

0x00_6010_0000

0x00_6011_FFFF

128 KB

AXI

Yes

Yes

Yes

FPGA Block RAM

0x00_6020_0000

0x00_63FF_FFFF

62 MB

-

N/C

N/C

N/C

Reserved

0x00_6400_0000

0x00_67FF_FFFF

64 MB

AXI

Yes

Yes

Yes

Spare AXI slave

0x00_6800_0000

0x00_6FFF_FFFF

128 MB

AXI

Yes

Yes

Yes

External SODIMM

0x00_7000_0000

0xFF_FFFF_FFFF

1022GB

TLX

AXI-S

N/C

N/C

Yes

Access to V2M-Juno

Table 2 Memory Map


6.2           SCC registers

Table 8 shows the location of the SCC registers in the example design.  The addresses shown are on APB bus offsets from the SCC base address 0x6001_0000.

 

Offset address

Name

Reset value

SIF Type

APB Type

Size

Function

0x000

SCC_USER0

0xXXXXXXXX

R/W

R/W

32

R/W register

0x004

SCC_USER1

0xXXXXXXXX

R/W

R/W

32

R/W register

0x100

SCC_DLLLOCK

0xFFXX000X

R/W

R

32

DLL locked

0x104

SCC_LED

0x0000000F

R

R/W

8

User LEDs control register

0x108

SCC_SW

0x000000XX

R/W

R

8

User Switches register

0xFF8

SCC_AID

0xXXXX0302

R/W

R

32

Auxiliary ID

0xFFC

SCC_ID

0x41X0415X

R/W

R

32

System ID

Table 3 Serial Configuration Control registers

6.2.1        SCC_USERx registers

The registers SCC_USER0 and SCC_USER1 (at offset 0x000-0x004) are general purpose user registers initialized during power up sequence by values from the daughter board configuration file.

In an existing AN415 build these registers can be used for any purpose by software.

 

Bits

Name

Access

Function

Default

[31:0]

SCC_USERx[31:0]

Read/write

General purpose registers configured during power up from configuration file

hXXXXXXXX

Table 4 SCC_USERx bit pattern


6.2.2        DLL lock register

The lock register SCC_DLLLOCK (at offset 0x100) indicates if all the DLLs in the system are locked.

Bits

Name

Access

Function

Default

[31:24]

DLL LOCK MASK[7:0]

Read

These bits indicate if the DLL locked is masked.

8’b11111111

[23:21]

DLL LOCK[7:5]

Read

These bits indicate if the DLLs are locked or unlocked:

b0 = unlocked

b1 = locked

8’b111xxxxx

[20]

DLL LOCK[4]

Read

Indicates if the DDR memory controller PLLs are locked

1’bx

[19]

DLL LOCK[3]

Read

Indicates if the PLL for the internal Thin Links clocks is locked

1’bx

[18]

DLL LOCK[2]

Read

Indicates if the PLL for the external Thin Links master clock is locked

1’bx

[17]

DLL LOCK[1]

Read

Indicates if the PLL for the external Thin Links slave clock is locked

1’bx

[16]

DLL LOCK[0]

Read

Indicates if the DDR memory controller has completed calibration

1’bx

[15:1]

Reserved

Reserved

Reserved

15’b0

[0]

LOCKED

Read

This bit indicates if all enabled DLLs are locked:

b0 = unlocked

b1 = locked

1’bx

Table 5 SCC_DLLLOCK bit pattern

6.2.3        User LEDs control register

 

The SCC_LED register (at offset 0x104) controls the 8 user LEDs on the V2F-1XV7 daughterboard.

Writing the value b11111111 will light all 8 LEDs.  LEDs can be lit individually, for example writing b00000011 will light only the LED0 and LED1.

 

Bits

Name

Access

Function

Default

[31:8]

Reserved

Read

Reserved

hXXXXXX

[7:0]

LED[7:0]

Read/Write

These bits control LEDs 

h0f

Table 6 SCC_LED bit pattern

 

6.2.4        User switches register

 

The SCC_SW register (at offset 0x108) indicates the state of the 8 of user switches on the V2F-1XV7 daughterboard.

 

Bits

Name

Access

Function

Default

[31:8]

Reserved

Read

Reserved

hXXXXXX

[7:0]

SW[7:0]

Read

These bits indicate state of user switches 

hXX

Table 7 SCC_SW bit pattern

6.2.5        SCC_AID register

The SCC_AID register (at offset 0xff8) includes the 16-bit SCC registers description.

 

Bits

Name

Access

Function

Default

[31:24]

Build

Read

FPGA build number

hXX

[23:16]

Reserved

Read

Reserved

hXX

[15:11]

Reserved

Read

Reserved

5’b00000

[10]

SWREGP

Read

These bits indicate if SCC_SW register has been implemented

1’b1

[9]

LEDREGP

Read

These bits indicate if SCC_LED register has been implemented

1’b1

[8]

DLLREGP

Read

These bits indicate if DLL lock register has been implemented

1’b1

[7:0]

USERREGN

Read

These bits indicate number of SCC_USERx registers

h02

Table 8 SCC_AID bit pattern

6.2.6        SCC_ID registers

The SCC_ID register (at offset 0xffc) includes the 32-bit AN identification.

 

Bits

Name

Access

Function

Default

[31:24]

Implementer

Read

Implementer ID

h41

[23:20]

Variant

Read

Variant

Number

hX

[19:16]

Architecture

Read

Architecture. Must be 0x0 for Application Notes.

h00

[15:4]

AN

Read

Application Note number

h415

[3:0]

Revision

Read

Revision number

hX

Table 9 SCC_ID bit pattern

6.3           Reserved and undefined memory

If reserved memory is accessed, it is caught by the AXI bus matrix and returns a decode error (‘DECERR’) which generates a data abort. The Spare AXI and APB busses are an exception and will ignore any accesses.

 

7   RTL

Only the top level and SCC RTL files are included.  AXI components are supplied as netlists. However, Amba Designer XML configuration files are provided for those components to allow them to be rebuilt. 

Example files are provided to allow building the system with Xilinx tools.

7.1           Directory structure

The application note has several directories.  They are:

      amba_designer:  XML configuration files provided to rebuild the NIC400.

      boardfiles:  The files are required to program the design into a V2F-1XV7.

      docs:  Related documents including this document.

      logical:  Verilog RTL for this design.

      physical:  Synthesis and place and route (P&R) scripts and builds for target board.

      software:  ARM code to exercise the AN415 application note.

7.2           Logical

The logical directory contains all the verilog supplied with this application note.  It also contains Amba Designer XML configuration files which can be used to regenerate verilog for ARM PrimeCell used in the example design.  

The top level for this system is in V2F_1XV7_wrapper.

7.3           Physical

The physical directory contains pre-synthesized components.  The function of each block is shown earlier in 4-3 Module functionality.

Each PrimeCell or other large IP block has its own directory (for example ds703_scc_r0p3).

The tool revisions used to build the App Note are listed in the /docs/readme.txt file.

7.4           Building the App Note using Linux

Building the application note is a two stage process.  Firstly the Xilinx memory controller black box must be built, then the application note.

7.4.1        Building the Xilinx memory controller

The Xilinx MIG 7 series 2.0 memory controller must be built with Xilinx Vivado 2013.4.

All settings for the configured controller are available in file:

AN415/physical/xilinx_mig_2_0/datasheet.txt.

All pin information is available in file:

AN415/physical/xilinx_mig_2_0/mig_pinout.ucf.

To create the MIG black box, create a new project in the AN415/physical/xilinx_mig_2_0/ directory.  Set the FPGA to xc7v2000tflg1925-1.

Select MIG 7 Series from the IP Catalog and configure it with default options unless noted below. If in doubt, refere to the supplied datasheet.txt.

Box

Item

Value

Component Name

Component Name

mig_7series_2_0

AXI4 Interface

AXI4 Interface

Options for Controller 0 – DDR3 SDRAM

Clock Period

2500ps

Options for Controller 0 – DDR3 SDRAM

Memory type

SODIMMs

Options for Controller 0 – DDR3 SDRAM

Memory part

MT8KTF51264HZ-1G6

Options for Controller 0 – DDR3 SDRAM

Ordering

Strict

AXI Parameter Options C0 – DDR3_SDRAM

Data Width

128

AXI Parameter Options C0 – DDR3_SDRAM

ID Width

16

Memory Options for Controller 0 – DDR3 SDRAM

Input Clock Period

10000 ps (100MHz)

System Clock

System Clock

Single-Ended

Pin/Bank Selection Mode

 

Fixed Pin Out

Pin Selection For Controller 0 – DDR3 SDRAM

Read XDC/UCF

mig_pinout.ucf

System Clock Pin Selection

sys_clk_i - bank

31

System Clock Pin Selection

sys_clk_i – pin

AU12(MRCC_P)

Reference Clock Pin Selection

clk_ref_p/n – bank

32

Reference Clock Pin Selection

clk_ref_p/n – pin

AT15/AU15(CC_P/N)

Table 10 Xilinx MIG settings

Click Generate at the end of the configuration menu.

In the Generate Output Products menu, first enter the  Out-of-Context  Settings menu, untick mig_7series_2_0.xcl, click OK (and OK on the warning dialogue) then click Generate.

In Project Manager, click Run Synthesis.

Select Open Synthesized Design in the Synthesis Completed dialogue.

In the TCL console type write_edif mig_7series_2_0.edf

Copy mig_7series_2_0.edf to the AN415/physical/blackboxes directory.


 

7.4.2        Building the application note

AN415 must be built with Xilinx Vivado 2013.4.

To build the App Note using Linux, run the make_vivado.scr batch file in the following directory: /physical/an415_toplevel/xilinx_revx/scripts .

This synthesizes the design and runs place and route on the design pulling in pre synthesized components.

A programmable bit file is generated under /physical/an415_toplevel/xilinx_revx/netlist called an415_wrapper.bit 

7.5           Using the new bitfile

To use the new an415_wrapper.bit bit file, the file must be copied to SITE2/HBI0262x/AN415 on the V2M-Juno USB Flash drive. It must be given a name in 8.3 character format such as a415user.bit. The configuration file a415r0p1.txt must be copied and renamed to match the bit file. For example copy a415r0p1.txt to a415user.txt.

The board.txt text file located at /SITE2/HBI0262x/ on the V2M-Juno USB Flash disk must be edited and the APPNOTE field must be modified to AN415/a415user.txt.

8   Example software

Example software (Selftest) is provided to verify the example design and the V2F-1XV7 daughterboard hardware.

C and assembly language source files are included.

After the Versatile Express system is configured you can upload and execute the example software using a debugger connected to the V2M-Juno motherboard.

The example code communicates with the user via the debugger’s console window. It operates as follows:

1.    Reads the identification register to ensure that the software is being executed on the correct system.

2.    Detects presence of DDR3 SODIMM (serial presence-detect (SPD) EEPROM).

3.    Tests the FPGA SRAM for sequential write/read and random write/read for word, half-word and byte accesses.

4.    Tests the DDR3 SDRAM for sequential write/read and random write/read for word, half-word and byte accesses.

5.    Tests the DMA controller and interrupt signal from DMA to the V2M-Juno motherboard.

9   I/O Timing Requirements

All of these specific timing requirements refer to the r0p2 revision of the AN415. All units are in nano-seconds “ns” and have been rounded to a worst case value.

Signals with setup, hold and clock to data values are bidirectional signals or have been grouped by function in the table.

9.1           Default, minimum and maximum operating frequencies

Clock

Oscillator

Minimum frequency

Default Frequency

Maximum Frequency

ACLK

OSC0

10.0

100.0

100.0

TLX

OSC1

20.0

61.5

61.5

DDR SYS CLK

OSC2

100.0

100.0

100.0

Not used

OSC3

N/A

30.0

N/A

Not used

OSC4

N/A

40.0

N/A

Not used

OSC5

N/A

70.0

N/A

DDR REF CLK

OSC6

200.0

200.0

200.0

TMIF_CLKO

Set by Juno board

20.0

61.5

61.5

TSIF_CLKO

Set by Juno board

20.0

61.5

61.5

Table 11 Operating Frequencies

Frequencies above the default frequency are not supported.

9.2           Thin Links timing requirements

The Thin Links interfaces in both directions operate as a DDR interface with clock transition in the center of the data eye.

Input timing requirements

Tsu

1.2ns

Minimum data setup time before clock edge.

Th

1.0ns

Minimum data hold time after clock edge.

Table 12 Input Timing Requirements

Output timing requirements

Tco-min

2.5ns

Data is available on the bus between Tco-min and Tco-max.

Tco-max

-2.5ns

Data is available on the bus between Tco-min and Tco-max.

Table 13 Output Timing Requirements

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