3.4.1. Memory management

In ARMv5, you can specify the memory access behavior of pages by configuring whether the cache and write buffer can be used for that location. This scheme is inadequate for more complex systems and processors. Therefore, ARMv7 adds the following mutually exclusive memory types:

Table 3.2 summarizes the memory attributes in ARMv7.

Table 3.2. Memory attributes summary

Memory type

Shareable/

Non-shareable

CacheableDescription
NormalShareable

Yes

Designed to handle normal memory that is shared among multiple cores.
Non-shareable

Yes

Designed to handle normal memory that is used only by a single core.
Device-NoDesigned to handle memory-mapped peripherals. All memory accesses to Device memory occur in program order.

Strongly-ordered

-NoAll memory accesses to Strongly-ordered memory occur in program order. All Strongly-ordered accesses are assumed to be shared.

In addition, ARMv7 supports the following memory attributes:

Page size support

In ARMv5, the following page sizes are supported:

  • 1KB.

  • 4KB.

  • 64KB.

In ARMv7-A without the LPAE implementation, the following page sizes are supported:

  • 4KB.

  • 64KB.

In ARMv7-A with the LPAE implementation, the following page sizes are supported:

  • 4KB.

  • 64KB.

  • 1MB.

  • 2MB.

  • 1GB.

Note

The 1KB page size is no longer supported in ARMv7.

Short-descriptor format

In ARMv7-A, Short-descriptor format is the only format supported on implementations that do not include the LPAE extension.

The Short-descriptor format uses 32-bit descriptor entries in the translation tables, and includes the following features:

  • Up to two levels of address lookup.

  • 32-bit input addresses.

  • Support for Physical Addresses (PAs) of more than 32 bits by use of supersections, with 16MB granularity.

  • Support for No access, Client, and Manager domains.

  • 32-bit table entries.

Each entry in the first-level table describes the mapping of the associated 1MB MVA range. Figure 3.5 shows the possible first-level descriptor formats:

Figure 3.5. Short-descriptor first-level descriptor formats

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Figure 3.6 shows the possible formats of a second-level descriptor:

Figure 3.6. Short-descriptor second-level descriptor formats

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The following points describe the descriptor fields, with the exception of the descriptor type field and the address field:

TEX[2:0], C, B

Memory region attribute bits.

These bits are not present in a Page table entry.

XN bit

The Execute-never bit, which determines whether the processor can execute software from the addressed region.

This bit is not present in a Page table entry.

PXN bit

The Privileged Execute-never bit, when supported, determines whether the processor can execute software from the region when executing at PL1.

NS bit

Non-secure bit, which specifies whether the translated PA is in the Secure or Non-secure address map.

Note

This bit is not present in second-level descriptors, and it is only applicable when CPU is in Secure state.

Domain

Domain field.

This field is not present in a Supersection entry. This bit is not present in second-level descriptors.

AP[2], AP[1:0]

Access Permissions bits.

These bits are not present in a Page table entry.

S bit

The Shareable bit, which determines whether the addressed region is Shareable memory.

This bit is not present in a Page table entry.

nG bit

The Not Global bit, which determines how the translation is marked in the TLB.

This bit is not present in a Page table entry.

Bit[18], when bits[1:0] indicate a Section or Supersection descriptor

0 - Descriptor is for a Section.

1 - Descriptor is for a Supersection.

Large Physical Address Extension

ARMv7-A introduces the LPAE extension. The LPAE provides an address translation system supporting physical addresses of up to 40 bits at a fine grain of translation. To do this, LPAE uses the Long-descriptor format.

The Virtualization Extensions provide an additional second stage of address translation when running virtual machines. The first stage of this translation produces an Intermediate Physical Address (IPA) and the second stage then produces the physical address, as shown in Figure 3.19. The second stage of this translation process is configured and controlled by the Hypervisor. In addition to an Address Space ID (ASID), TLB entries can also have an associated Virtual Machine ID (VMID). You can also disable the stage 2 MMU and have a flat mapping from IPA to PA.

The Long-descriptor format uses 64-bit descriptor entries in the translation tables, and includes the following features:

  • Up to three levels of address lookup.

  • Input addresses of up to 40 bits, when used for stage 2 translations.

  • Output addresses of up to 40 bits.

  • 4KB assignment granularity across the entire PA range.

  • No support for domains, all memory regions are treated as in a Client domain.

  • 64-bit table entries.

  • Fixed 4KB table size, unless truncated by the size of the input address space.

In the Long-descriptor translation tables, the formats of the first-level and second-level descriptors differ only in the size of the block of memory addressed by the block descriptor. Figure 3.7 shows the Long-descriptor first-level and second-level descriptor formats:

Figure 3.7. Long-descriptor first-level and second-level descriptor formats

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Each entry in a third-level table describes the mapping of the associated 4KB input address range. Figure 3.8 shows the Long-descriptor third-level descriptor formats:

Figure 3.8. Long-descriptor third-level descriptor formats

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MMU registers

Compared with ARMv5, ARMv7-A has much larger MMU registers. Table 3.3 shows an overview of all new or changed MMU registers, in coprocessor register number order.

For detailed information about these registers, see section B3.17 Organization of the CP15 registers in a VMSA implementation in the ARM® Architecture Reference Manual ARMv7-A and ARMv7-R Edition, ARM DDI 0406C.

Table 3.3. New or changed MMU registers

NameNew or ChangedWidthDescription
SCTLRChanged32-bitSystem Control Register
ACTLRNew32-bitIMPLEMENTATION DEFINED Auxiliary Control Register
CPACRNew32-bitCoprocessor Access Control Register
SCRNew32-bitSecure Configuration Register
SDERNew32-bitSecure Debug Enable Register
NSACRNew32-bitNon-secure Access Control Register
HSCTLRNew32-bitHypervisor System Control Register
HACTLRNew32-bitHypervisor Auxiliary Control Register
HCRNew32-bitHypervisor Configuration Register
HDCRNew32-bitHypervisor Debug Configuration Register
HCPTRNew32-bitHypervisor Coprocessor Trap Register
HSTRNew32-bitHypervisor System Trap Register
HACRNew32-bitHypervisor Auxiliary Configuration Register
TTBR0New32-bitTranslation Table Base Register 0
TTBR0New64-bitTranslation Table Base Register 0
TTBR1New32-bitTranslation Table Base Register 1
TTBR1New64-bitTranslation Table Base Register 1
TTBCRNew32-bitTranslation Table Base Control Register
HTCRNew32-bitHypervisor Translation Control Register
VTCRNew32-bitVirtualization Translation Control Register
HTTBRNew32-bitHypervisor Translation Table Base Register
VTTBRNew32-bitVirtualization Translation Table Base Register
DFSRNew32-bitData Fault Status Register
IFSRNew32-bitInstruction Fault Status Register
ADFSRNew32-bitAuxiliary Data Fault Status Register
AIFSRNew32-bitAuxiliary Instruction Fault Status Register
HADFSRNew32-bitHypervisor Auxiliary Data Fault Syndrome Register
HAIFSRNew32-bitHypervisor Auxiliary Instruction Fault SyndromeRegister
HSRNew32-bitHypervisor Syndrome Register
DFARNew32-bitData Fault Address Register
IFARNew32-bitInstruction Fault Address Register
HDFARNew32-bitHypervisor Data Fault Address Register
HIFARNew32-bitHypervisor Instruction Fault Address Register
HPFARNew32-bitHypervisor IPA Fault Address Register
PARNew32-bitPhysical Address Register
PARNew64-bitPhysical Address Register
PRRRNew32-bitPrimary Region Remap Register
MAIR0New32-bitMemory Attribute Indirection Register 0
NMRRNew32-bitNormal Memory Remap Register
MAIR1New32-bitMemory Attribute Indirection Register 1
AMAIR0New32-bitAuxiliary Memory Attribute IndirectionRegister 0
AMAIR1New32-bitAuxiliary Memory Attribute IndirectionRegister 1
HMAIR0New32-bitHypervisor Memory Attribute Indirection Register 0
HMAIR1New32-bitHypervisor Memory Attribute Indirection Register 1
HAMAIR0New32-bitHypervisor Auxiliary Memory Attribute IndirectionRegister 0
HAMAIR1New32-bitHypervisor Auxiliary Memory Attribute IndirectionRegister 1
VBARNew32-bitVector Base Address Register
MVBARNew32-bitMonitor Vector Base Address Register
ISRNew32-bitInterrupt Status Register
HVBARNew32-bitHypervisor Vector Base Address Register
FCSEIDRNew32-bitFCSE Process ID Register
CONTEXTIDRNew32-bitContext ID Register
TPIDRURWNew32-bitUser Read/Write Thread ID Register
TPIDRURONew32-bitUser Read-Only Thread ID Register
TPIDRPRWNew32-bitPL1 only Thread ID Register
HTPIDRNew32-bitHypervisor Software Thread ID Register

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