3.12. MP-core cache coherency

Cache coherency ensures that all processors or bus masters in the system have the same view of memory. It means that changes to data in the cache of one core are visible to other cores, making it impossible for cores to see stale copies of the data.

In ARMv7-A, there are three mechanisms to maintain cache coherency:

Copyright © 2014 ARM. All rights reserved.ARM DAI0425
Non-ConfidentialID080414