4.2.6. Fault handling

In ARMv5, the registers Fault Status Register (FSR) and Fault Address Register (FAR) investigate the cause of aborts resulting from data accesses, known as Data Aborts. It is implementation-defined whether the FSR and FAR are updated for an abort arising from an instruction fetch, and if so, what useful information they contain about the fault.

Aborts are further classified into data aborts and prefetch aborts. ARMv7 can differentiate whether an abort is generated either on failed instruction fetches, known as prefetch aborts, or on failed data accesses, known as data aborts. Therefore, the following registers are provided to indicate the cause of aborts:

DFAR

The DFAR holds the virtual address of the faulting address that caused a synchronous Data Abort exception.

DFSR

The DFSR holds status information about the last data fault.

IFAR

The IFAR holds the address of the access that caused a synchronous Prefetch Abort exception.

IFSR

The IFSR holds status information about the last instruction fault.

The encodings of FAR and FSR in ARMv5 are different from those of DFAR and DFSR, or IFAR and IFSR, in ARMv7.

For more information about the encodings of DFAR, FDSR, IFAR, and IFSR, see the VMSA System control registers section in the ARM® Architecture Reference Manual ARMv7-A and ARMv7-R Edition, ARM DDI 0406C.

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