4.4. Replacing ARMv5 synchronization primitives with equivalent ARMv7 synchronization primitives

In ARMv7, the SWP and SWPB instructions are deprecated, you must replace them with equivalent ARMv7 synchronization primitives in source code.

ARMv7 provides the following instructions relating to exclusive access. Variants of these instructions are also provided to operate on byte, halfword, word, or doubleword sized data. The instructions rely on the ability of the core or memory system to tag particular addresses to be monitored for exclusive accesses by that core, using an exclusive access monitor.

Only perform Load-Exclusive and Store-Exclusive operations on Normal memory. The operations have slightly different effects, depending on whether the memory is marked as Shareable. If the core reads from Shareable memory with an LDREX, the load occurs and that physical address is tagged to be monitored for exclusive access by that core. If any other core writes to that address and the memory is marked as Shareable, the tag is cleared.

If the memory is not Shareable, any attempt to write to the tagged address by the one that tagged it causes the tag to be cleared. If the core performs an additional LDREX to a different address, the tag for the previous LDREX address is cleared. Each core can only have one address tagged.

STREX can be considered as a conditional store. The store is performed only if the physical address is still marked as exclusive access. This means that it was previously tagged by this core and no other core has since written to it. STREX returns a status value showing if the store succeeded. STREX always clears the exclusive access tag.

The use of these instructions is not limited to multi-core systems. In fact, they are frequently used in single-core systems, to implement synchronization operations among threads running on the same core.

In hardware, the core includes a device named the local monitor. This monitor observes the core. When the core performs an exclusive load access, it records that fact in the local monitor. When it performs an exclusive store, it checks that a previous exclusive load was performed and fails the exclusive store if this was not the case. The architecture enables individual implementations to determine the level of checking performed by the monitor. The core can only tag one physical address at a time. An LDREX from a particular address can be followed shortly after by an STREX to the same location, before an LDREX from a different address is performed. This is because the local monitor does not have to store the address of the exclusive tag. However, it can do so if the processor is implemented to do this. The architecture enables the local monitor to treat any exclusive store as matching a previous LDREX address. For this reason, use of the CLREX instruction to clear an existing tag is required on context switches.

Where you use exclusive accesses to synchronize with external masters outside the core, or to regions marked as Shareable even between cores in the same cluster, you must implement a global monitor within the hardware system. This acts as a wrapper to one or more memory slave devices and is independent of the individual cores. This is specific to a particular SoC and might not exist in any particular system. An LDREX and STREX sequence performed to a memory location that has no suitable exclusive access monitor fails, with the STREX instruction always returning 1.

Example 4.6 shows the use of the LDREX and STREX instructions.

Example 4.6.  Spin-lock

	; void lock(lock_t* pAddr)
lock
	; Is locked?
 	LDREX   r1, [r0] 							; Check if locked.
	CMP     r1, #LOCKED         ; Compare with “locked“.
	BEQ     lock 							; If LOCKED, try again.

	; Attempt to lock
	MOV     r1, #LOCKED
	STREX   r2, r1, [r0]        ; Attempt to lock.
	CMP     r2, #0x0 							; Check whether store completed.
	BNE     lock 							; If store failed, try again.
	DMB
	BX      lr

Copyright © 2014 ARM. All rights reserved.ARM DAI0425
Non-ConfidentialID080414