3.1.2. System control coprocessor registers

In ARMv7-A, the following system control coprocessor registers are different from those in ARMv5:

CP15 c0, Cache Type Register

In ARMv5, the format of the Cache Type Register is different from the ARMv7-A definition. However, the general properties described by the register, and the access rights for the register, remain unchanged.

Figure 3.2 shows the bit assignments of the Cache Type Register in ARMv5 and ARMv7-A.

Figure 3.2. Bit assignments of Cache Type Register in ARMv5 and ARMv7-A

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Bits[31:29] indicate the CTF format. In ARMv5, you can specify only one value, 0b000, which indicates the ARMv5 and ARMv6 format. In ARMv7-A, you can add another value, 0b100, to indicate the ARMv7 format.

The following points describe the descriptor fields for the Cache Type Register in an ARMv7 VMSA implementation:

Format, bits[31:29]

Indicates the implemented CTR format.

Bit[28]

RAZ.

CWG, bits[27:24]

Cache Write-back Granule.

ERG, bits[23:20]

Exclusives Reservation Granule.

DminLine, bits[19:16]

Log2 of the number of words in the smallest cache line of all the data caches and unified caches that are controlled by the processor.

L1Ip, bits[15:14]

Level 1 instruction cache policy. Indicates the indexing and tagging policy for the L1 instruction cache.

Bits[13:4]

RAZ.

IminLine, bits[3:0]

Log2 of the number of words in the smallest cache line of all the instruction caches that are controlled by the processor.

CP15 c1, System Control Register

Figure 3.3 shows the bit assignments of the System Control Register in ARMv5 and ARMv7-A.

Figure 3.3. Bit assignments of System Control Register in ARMv5 and ARMv7

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The following usage models in ARMv5 are not compatible with ARMv7-A:

  • Bits[31:16] Reserved, UNK/SBZP.

  • The following reserved bits in the SCTLR are allocated in certain circumstances:

    • Bits[19:16] can be associated with TCM support.

    • Bit[26], described as the L2 bit, can indicate level 2 cache support.

From ARMv6, ARM deprecates any use of the following features, and ARMv7-A does not support these features:

L4, bit [15]

When set, this bit inhibits ARMv5T Thumb interworking behavior when set. It stops bit[0] updating the CPSR.T bit.

R, bit [9]

ROM protection bit, supported for backwards compatibility.

S, bit[8]

System protection bit, supported for backwards compatibility.

B, bit[7]

This bit configures the ARM processor to the endianness of the memory system:

  • 0 Little-endian memory system (LE).

  • 1 Big-endian memory system (BE-32).

W, bit[3]

It is the enable bit for the write buffer:

  • 0 Write buffer disabled.

  • 1 Write buffer enabled.

CP15 c13, VMSA FCSE support

The Fast Context Switch Extension (FCSE) is an implementation-defined option in ARMv5. The feature is supported by the FCSEIDR. ARMv7-A supports FCSEIDR.

The ARMv7-A Context ID and Software Thread ID registers are not supported in ARMv5.

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