3.7.1. Dual Translation Tables

In ARMv7-A, you can split the 32-bit virtual address space into two regions, one for user application and the other one for kernel mapping. The application space changes on each context switch, but the kernel space is likely to remain static.

On a task switch, you must update the page tables to those for the newly switched task. You can do this by rewriting the existing page table, or by changing the TTBR to point to a different table. However, rewriting the table takes time, and changing to a different table would duplicate the OS portion of the table each time.

To avoid these problems, you use Virtual Memory System Architecture (VMSA), which split the virtual address space across two L1 tables. The TTBR1 register points to one table containing the kernel-related translations, and this table remains constant across task switches. The other table contains the application-specific space. Each process has its own table, with TTBR0 redirected to the appropriate table on a task switch.

Copyright © 2014 ARM. All rights reserved.ARM DAI0425
Non-ConfidentialID080414