2.1. ARMv7 architecture overview

ARMv7 is implemented in the Cortex range of processors, and is defined in the following three profiles:

The following optional extensions to the ARMv7-A architecture are available:

Security

The TrustZone® security extension was introduced in the v6K architecture and is an optional extension to the ARMv7-A profile. TrustZone introduces an additional operating mode, Monitor (Mon) mode, with associated banked registers and an additional “Secure” operating state.

Advanced SIMD and Floating Point

Both floating point (VFP) support and Advanced SIMD (NEON) are optional extensions to the ARMv7-A profile. They can be implemented together, in which case they share a common register bank and some common instructions. Almost all NEON implementations also include floating point support.

40-bit physical addressing

LPAE is an optional extension to the ARMv7-A profile. This extension to the VMSAv7 virtual memory architecture enables the generation of 40-bit physical addresses from 32-bit virtual addresses. LPAE is supported by the Cortex-A7, Cortex-A12, Cortex-A15, and Cortex-A17 processors.

Virtualization

The virtualization extension introduces an extra mode, Hypervisor mode, with associated banked registers. You can use a new Hyp exception to trap software accesses to hardware and configuration registers, thus enabling the implementation of an efficient hardware-assisted virtualization solution. This extension is supported by the Cortex-A7, Cortex-A12, Cortex-A15, and Cortex-A17 processors.

For more information about these extensions, see ARM® Architecture Reference Manual ARMv7-A and ARMv7-R Edition, ARM DDI 0406C.

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