3.6.1. Cache

The cache differences between ARMv5 and ARMv7-A are in the following areas:

Data cache type

In ARMv5, data cache is organized as a Virtually-indexed, Virtually-tagged (VIVT) cache, in which both the index and the tag are based on the virtual address. This caching method can require the cache to be flushed when virtual address to physical address mappings are changed.

In ARMv7-A, data cache is organized as Physically-indexed, Physically-tagged (PIPT), in which both the index and the tag are based on the physical address. PIPT cache is simple and avoids problems with aliasing.

Data cache clean on context switches

In ARMv5, you might need to perform a data cache clean on context switches. In ARMv7-A, there is no need to perform a data cache clean on context switches.

Note

A context switch means that the scheduler transfers execution from one process to another. This typically requires saving the current process state and restoring the state of the next process waiting to be run.

Cache behavior at reset

In ARMv5, cache is invalidated by hardware at reset. In ARMv7-A, cache invalidation by hardware is implementation-defined.

L2 cache support

Existing ARMv5 processors do not support the L2 cache, while ARMv7-A can support the L2 cache.

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