3.6.2. Translation Lookaside Buffers

Full translation table lookup is performed automatically by hardware, and has a significant execution-time cost. To reduce the average cost of a memory access, the results of translation table walks are cached in one or more structures known as Translation Lookaside Buffers (TLBs).

In ARMv5, you must invalidate the entire TLBs on context switches. However, ARMv7-A introduces support for Address Space IDs (ASIDs), and does not need to invalidate the entire TLBs on context switches. For more information about ASIDs, see Address Space Identifiers.

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