3.12.1. MESI and MOESI protocols

Cache coherency schemes operate in a number of standard ways. Most ARM processors use the Modified Owner Exclusive Shared Invalid (MOESI) protocol, while Cortex-A9 uses the Modified Exclusive Shared Invalid (MESI) protocol.

Based on the protocol in use, the Snoop Control Unit (SCU) marks each line in the cache with one of the following attributes:

Figure 3.22 shows the use of the MESI protocol in memory and cache.

Figure 3.22.  MESI state in memory and cache

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