3.12.2. Snoop Control Unit

Figure 3.23 shows how the Snoop Control Unit (SCU) maintains coherency among the L1 data cache of each core. The SCU arbitrates accesses to L2 AXI master interfaces, for both instructions and data. Duplicated Tag RAMs track what data is allocated in each CPU cache.

Because executable code changes much less frequently, this functionality is not extended to the L1 instruction caches. The coherency management is implemented using a MOESI-based protocol, optimized to decrease the number of external memory accesses.

Figure 3.23. Snoop Control Unit

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.

To enable coherency management for a memory access, all of the following conditions must be true:

The SCU can only maintain coherency within a single cluster.

Copyright © 2014 ARM. All rights reserved.ARM DAI0425