ARM7TDMI Technical Reference Manual 3.6.3. Byte latch enables

3.6.3. Byte latch enables

To ease the connection of the ARM7TDMI core to sub-word sized memory systems, input data and instructions can be latched on a byte-by-byte basis. This is achieved by the use of the BL[3:0] signal as follows:

BL[3] controls the latching of the data present on D[31:24]
BL[2] controls the latching of the data present on D[23:16]
BL[1] controls the latching of the data present on D[15:8]
BL[0] controls the latching of the data present on D[7:0].

Note

It is recommended that BL[3:0] is tied HIGH in new designs and word values from narrow memory systems are latched onto latches that are external to the ARM7TDMI core.

In a memory system that only contains word-wide memory, BL[3:0] can be tied HIGH. For sub-word wide memory systems, the BL[3:0] signals are used to latch the data as it is read out of memory. For example, a word access to halfword wide memory must take place in two memory cycles:

in the first cycle, the data for D[15:0] is obtained from the memory and latched into the core on the falling edge of MCLK when BL[1:0] are both HIGH.
in the second cycle, the data for D[31:16] is latched into the core on the falling edge of MCLK when BL[3:2] are both HIGH and BL[1:0] are both LOW.

In Figure 3.18, a word access is performed from halfword wide memory in two cycles:

in the first cycle, the read data is applied to the lower half of the bus
in the second cycle, the read data is applied to the upper half of the bus.

Because two memory cycles are required, nWAIT is used to stretch the internal processor clock. nWAIT does not affect the operation of the data latches. Using this method, data can be taken from memory as word, halfword, or byte at a time and the memory can have as many wait states as required. In multi-cycle memory accesses, nWAIT must be held LOW until the final part is latched.

In the example shown in Figure 3.18, the BL[3:0] signals are driven to value 0x3 in the first cycle so that only the latches on D[15:0] are open. BL[3:0] can be driven to value 0xF and all of the latches opened. This does not affect the operation of the core because the latches on D[31:16] are written with the correct data during the second cycle.

Note

BL[3:0] must be held HIGH during store cycles.

Figure 3.18. Memory access

Figure 3.19 shows a halfword load from single-wait state byte wide memory. In the figure, each memory access takes two cycles:

in the first access:
- BL[3:0] are driven to 0xF
- the correct data is latched from D[7:0]
- unknown data is latched from D[31:8].
in the second cycle, the byte for D[15:8] is latched so the halfword on D[15:0] is correctly read from memory. It does not matter that D[31:16] are unknown because the core only extracts the halfword that it is interested in.

Figure 3.19. Two cycle memory access

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