ARM7TDMI Technical Reference Manual 7.24. Notes on AC Parameters

7.24. Notes on AC Parameters

Table 7.23 lists the AC timing parameters in alphabetical order.

Contact your supplier for AC timing parameter values.

the letter f at the end of a signal name indicates the falling edge
the letter r at the end of a signal name indicates the rising edge.

Table 7.23. AC timing parameters used in this chapter

Symbol	Parameter	Parameter Type	Figure cross reference
T_abe	Address bus enable time	Maximum	Figure 7.2
T_abth	ABORT hold time from MCLKf	Minimum	Figure 7.11
T_abts	ABORT set up time to MCLKf	Minimum	Figure 7.11
T_abz	Address bus disable time	Maximum	Figure 7.2
T_addr	MCLKr to address valid	Maximum	Figure 7.1 Figure 7.17
T_ah	Address hold time from MCLKr	Minimum	Figure 7.1
T_ald	Address group latch time	Maximum	Figure 7.22
T_ale	Address group latch open output delay	Maximum	Figure 7.22
T_aleh	Address group latch output hold time	Minimum	Figure 7.22
T_ape	MCLKf to address group valid	Maximum	Figure 7.23
T_apeh	Address group output hold time from MCLKf	Minimum	Figure 7.23
T_aph	APE hold time from MCLKf	Minimum	Figure 7.23
T_aps	APE set up time to MCLKr	Minimum	Figure 7.23
T_bcems	BREAKPT to nCPI, nEXEC, nMREQ, SEQ delay	Maximum	Figure 7.13
T_bld	MCLKr to MAS[1:0] and LOCK	Maximum	Figure 7.1
T_blh	MAS[1:0] and LOCK hold from MCLKr	Minimum	Figure 7.1
T_brkh	Hold time of BREAKPT from MCLKr	Minimum	Figure 7.13
T_brks	Set up time of BREAKPT to MCLKr	Minimum	Figure 7.13
T_bsch	TCK high period	Minimum	Figure 7.18
T_bscl	TCK low period	Minimum	Figure 7.18
T_bsdd	TCK to data output valid	Maximum	Figure 7.18
T_bsdh	Data output hold time from TCK	Minimum	Figure 7.18
T_bse	Output enable time	Maximum	Figure 7.20 Figure 7.21
T_bsih	TDI, TMS hold from TCKr	Minimum	Figure 7.18
T_bsis	TDI, TMS setup to TCKr	Minimum	Figure 7.18
T_bsod	TCKf to TDO valid	Maximum	Figure 7.18
T_bsoh	TDO hold time from TCKf	Minimum	Figure 7.18
T_bsr	nTRST reset period	Minimum	Figure 7.19
T_bssh	I/O signal setup from TCKr	Minimum	Figure 7.18
T_bsss	I/O signal setup to TCKr,	Minimum	Figure 7.18
T_bsz	Output disable time	Maximum	Figure 7.20 Figure 7.21
T_bylh	BL[3:0] hold time from MCLKf	Minimum	Figure 7.4 Figure 7.8
T_byls	BL[3:0] set up to from MCLKr	Minimum	Figure 7.4 Figure 7.8
T_cdel	MCLK to ECLK delay	Maximum	Figure 7.1
T_clkbs	TCK to boundary scan clocks	Maximum	-
T_commd	MCLKr to COMMRX, COMMTX valid	Maximum	Figure 7.14
T_cph	CPA,CPB hold time from MCLKr	Minimum	Figure 7.10
T_cpi	MCLKf to nCPI valid	Maximum	Figure 7.10
T_cpih	nCPI hold time from MCLKf	Minimum	Figure 7.10
T_cpms	CPA, CPB to nMREQ, SEQ	Maximum	Figure 7.10
T_cps	CPA, CPB setup to MCLKr	Minimum	Figure 7.10
T_ctdel	TCK to ECLK delay	Maximum	Figure 7.16
T_cth	Config hold time	Minimum	Figure 7.9
T_cts	Config setup time	Minimum	Figure 7.9
T_dbe	Data bus enable time from DBEr	Maximum	Figure 7.5
T_dbgd	MCLKr to DBGACK valid	Maximum	Figure 7.13
T_dbgh	DGBACK hold time from MCLKr	Minimum	Figure 7.13
T_dbgrq	DBGRQ to DBGRQI valid	Maximum	Figure 7.13
T_dbnen	DBE to nENOUT valid	Maximum	Figure 7.5
T_dbz	Data bus disable time from DBEf	Maximum	Figure 7.5
T_dckf	DCLK induced, TCKf to various outputs valid	Maximum	-
T_dckfh	DCLK induced, various outputs hold from TCKf	Minimum	-
T_dckr	DCLK induced, TCKr to various outputs valid	Maximum	-
T_dckrh	DCLK induced, various outputs hold from TCKr	Minimum	-
T_dih	DIN[31:0] hold time from MCLKf	Minimum	Figure 7.4
T_dihu	DIN[31:0] hold time from MCLKf	Minimum	Figure 7.8
T_dis	DIN[31:0] setup time to MCLKf	Minimum	Figure 7.4
T_disu	DIN[31:0] set up time to MCLKf	Minimum	Figure 7.8
T_doh	DOUT[31:0] hold from MCLKf	Minimum	Figure 7.3 Figure 7.5
T_dohu	DOUT[31:0] hold time from MCLKf	Minimum	Figure 7.7
T_dout	MCLKf to D[31:0] valid	Maximum	Figure 7.3 Figure 7.5
T_doutu	MCLKf to DOUT[31:0] valid	Maximum	Figure 7.7
T_ecapd	TCK to ECAPCLK changing	Maximum	-
T_exd	MCLKf to nEXEC valid	Maximum	Figure 7.1
T_exh	nEXEC hold time from MCLKf	Minimum	Figure 7.1
T_exth	EXTERN[1:0] hold time from MCLKf	Minimum	Figure 7.13
T_exts	EXTERN[1:0] set up time to MCLKf	Minimum	Figure 7.13
T_im	Asynchronous interrupt guaranteed nonrecognition time, with ISYNC=0	Maximum	Figure 7.11
T_is	Asynchronous interrupt set up time to MCLKf for guaranteed recognition, with ISYNC=0	Minimum	Figure 7.11
T_mckh	MCLK HIGH time	Minimum	Figure 7.17
T_mckl	MCLK LOW time	Minimum	Figure 7.17
T_mdd	MCLKr to nTRANS, nM[4:0], and TBIT valid	Maximum	Figure 7.1
T_mdh	nTRANS and nM[4:0] hold time from MCLKr	Minimum	Figure 7.1
T_msd	MCLKf to nMREQ and SEQ valid	Maximum	Figure 7.1 Figure 7.17
T_msh	nMREQ and SEQ hold time from MCLKf	Minimum	Figure 7.1
T_nen	MCLKf to nENOUT valid	Maximum	Figure 7.3 Figure 7.4 Figure 7.7 Figure 7.8
T_nenh	nENOUT hold time from MCLKf	Minimum	Figure 7.3
T_opcd	MCLKr to nOPC valid	Maximum	Figure 7.1
T_opch	nOPC hold time from MCLKr	Minimum	Figure 7.1
T_rg	MCLKf to RANGEOUT0, RANGEOUT1 valid	Maximum	Figure 7.13
T_rgh	RANGEOUT0, RANGEOUT1 hold time from MCLKf	Minimum	Figure 7.13
T_rm	Reset guaranteed nonrecognition time	Maximum	Figure 7.11
T_rqh	DBGRQ guaranteed non-recognition time	Minimum	Figure 7.13
T_rqs	DBGRQ set up time to MCLKr for guaranteed recognition	Minimum	Figure 7.13
T_rs	Reset setup time to MCLKr for guaranteed recognition	Minimum	Figure 7.11
T_rstd	nRESETf to D[31:0], DBGACK, nCPI, nENOUT, nEXEC, nMREQ, SEQ valid	Maximum	Figure 7.19
T_rstl	nRESET LOW for guaranteed reset	Minimum	Figure 7.19
T_rwd	MCLKr to nRW valid	Maximum	Figure 7.1
T_rwh	nRW hold time from MCLKr	Minimum	Figure 7.1
T_sdtd	SDOUTBS to TDO valid	Maximum	-
T_shbsf	TCK to SHCLKBS, SHCLK2BS falling	Maximum	-
T_shbsr	TCK to SHCLKBS, SHCLK2BS rising	Maximum	-
T_sih	Synchronous nFIQ, nIRQ hold from MCLKf with ISYNC=1	Minimum	Figure 7.12
T_sis	Synchronous nFIQ, nIRQ setup to MCLKf, with ISYNC=1	Minimum	Figure 7.12
T_tbe	Address and Data bus enable time from TBEr	Maximum	Figure 7.6
T_tbz	Address and Data bus disable time from TBEf	Maximum	Figure 7.6
T_tckf	TCK to TCK1, TCK2 falling	Maximum	-
T_tckr	TCK to TCK1, TCK2 rising	Maximum	-
T_tdbgd	TCK to DBGACK, DBGRQI changing	Maximum	-
T_tpfd	TCKf to TAP outputs	Maximum	-
T_tpfh	TAP outputs hold time from TCKf	Minimum	-
T_tprd	TCKr to TAP outputs	Maximum	-
T_tprh	TAP outputs hold time from TCKr	Minimum	-
T_trstd	nTRSTf to every output valid	Maximum	-
T_trstd	nTRSTf to TAP outputs valid	Maximum	-
T_trsts	nTRSTr setup to TCKr	Maximum	-
T_wh	nWAIT hold from MCLKf	Minimum	Figure 7.17
T_ws	nWAIT setup to MCLKr	Minimum	Figure 7.17

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