When BUSEN is HIGH, all instructions and input data are presented on the input data bus, DIN[31:0]. The timing of this data is similar to that of the bidirectional bus when in input mode. Data must be set up and held to the falling edge of MCLK. For the exact timing requirements refer to Chapter 7 AC and DC Parameters.

In this configuration, all output data is presented on DOUT[31:0]. The value on this bus only changes when the processor performs a store cycle. Again, the timing of the data is similar to that of the bidirectional data bus. The value on DOUT[31:0] changes after the falling edge of MCLK.

The bus timing of a read-write-read cycle combination is shown in Figure 3.13.

When the unidirectional data buses are being used, and BUSEN is HIGH, the bidirectional bus, D[31:0], must be left unconnected.

The unidirectional buses are typically used internally in ASIC embedded applications. Externally, most systems still require a bidirectional data bus to interface to external memory. Figure 3.14 shows how you can join the unidirectional buses up at the pads of an ASIC to connect to an external bidirectional bus.

When BUSEN is LOW, the buffer between DIN[31:0] and D[31:0] is disabled. Any data presented on DIN[31:0] is ignored. Also, when BUSEN is LOW, the value on DOUT[31:0] is forced to 0x00000000.

When the ARM7TDMI processor is reading from memory DIN[31:0] is acting as an input. During write cycles the ARM7TDMI core must output data. During phase 2 of the previous cycle, the signal nRW is driven HIGH to indicate a write cycle. During the actual cycle, nENOUT is driven LOW to indicate that the processor is driving D[31:0] as an output. Figure 3.15 shows the bus timing with the data bus enabled. Figure 3.16 shows the circuit that exists in the processor for controlling exactly when the external bus is driven out.

The macrocell has an additional bus control signal, nENIN that allows the external system to manually tristate the bus. In the simplest systems, nENIN can be tied LOW and nENOUT can be ignored. In many applications, when the external data bus is a shared resource, greater control might be required. In this situation, nENIN can be used to delay when the external bus is driven.

The processor has another output control signal called TBE. This signal is usually only used during test and must be tied HIGH when not in use. When driven LOW, TBE forces all tristateable outputs to high impedance, it is as though both DBE and ABE have been driven LOW, causing the data bus, the address bus, and all other signals normally controlled by ABE to become high impedance.

Table 3.6 lists the tristate control of the processor outputs.

Connecting the ARM7TDMI processor data bus, D[31:0] to an external shared bus requires additional logic that varies between applications in the case of a test chip.

In this application, care must be taken to prevent bus clash on D[31:0] when the data bus drive changes direction. The timing of nENIN, and the pad control signals must be arranged so that when the core starts to drive out, the pad drive onto D[31:0] is disabled before the core starts to drive. Similarly, when the bus switches back to input, the core must stop driving before the pad is enabled.

The circuit implemented in the ARM7TDMI processor test chip is shown in Figure 3.17.