ARM7TDMI Technical Reference Manual B.16. The debug status register

B.16. The debug status register

The debug status register is 5 bits wide. If it is accessed for a write, with the read/write bit set, the status bits are written. If it is accessed for a read, with the read/write bit clear, the status bits are read. The format of the debug status register is shown in Figure B.10.

Figure B.10. Debug status register format

The function of each bit in this register is as follows:

Bit 4: Enables TBIT to be read. This enables the debugger to determine the processor state and therefore which instructions to execute.
Bit 3: Enables the debugger to determine if a memory access from the debug state has completed.
Bit 2: Enables the state of the core interrupt enable signal, IFEN, to be read. Enables the state of the NMREQ signal from the core, synchronized to TCK, to be read. This enables the debugger to determine that a memory access from the debug state has completed.
Bits 1:0: Enable the values on the synchronized versions of DBGRQ and DBGACK to be read.

The structure of the debug control and status registers is shown in Figure B.11.

Figure B.11. Debug control and status register structure

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