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Table 2.4 lists the exception vector addresses. In this table, I and F represent the previous value of the IRQ and FIQ interrupt disable bits respectively in the CPSR.
Table 2.4. Exception vectors
Address | Exception | Mode on entry | I state on entry | F state on entry |
|---|---|---|---|---|
0x00000000 | Reset | Supervisor | Set | Set |
0x00000004 | Undefined instruction | Undefined | Set | Unchanged |
0x00000008 | Software interrupt | Supervisor | Set | Unchanged |
0x0000000C | Prefetch Abort | Abort | Set | Unchanged |
0x00000010 | Data Abort | Abort | Set | Unchanged |
0x00000014 | Reserved | Reserved | - | - |
0x00000018 | IRQ | IRQ | Set | Unchanged |
0x0000001C | FIQ | FIQ | Set | Set |
| Copyright © 1994-2001. All rights reserved. | ARM DDI 0029G |
| Non-Confidential | |
| PDF version | |
| Home > Programmer’s Model > Exceptions > Exception vectors |