The Fast Interrupt Request (FIQ) exception supports data transfers or channel processes. In ARM state, FIQ mode has eight banked registers to remove the requirement for register saving. This minimizes the overhead of context switching.

An FIQ is externally generated by taking the nFIQ input LOW. The input passes into the core through a synchronizer.

Irrespective of whether exception entry is from ARM state or from Thumb state, an FIQ handler returns from the interrupt by executing:

SUBS PC,R14_fiq,#4

FIQ exceptions can be disabled within a privileged mode by setting the CPSR F flag. When the F flag is clear, the ARM7TDMI processor checks for a LOW level on the output of the FIQ synchronizer at the end of each instruction.