Figure 7.5 shows
the ARM7TDMI data bus control timing. The timing parameters used in Figure 7.5 are listed in Table 7.5.
Note
The cycle shown in Figure 7.5 is a data write cycle because nENOUT was driven LOW during phase
one. Here, DBE has first been
used to modify the behavior of the data bus, and then nENIN.
Table 7.5. Data bus control timing parameters
| Symbol | Parameter | Parameter type |
|---|
| Tdbe | Data bus enable time from DBEr | Maximum |
| Tdbnen | DBE to nENOUT valid | Maximum |
| Tdbz | Data bus disable time from DBEf | Maximum |
| Tdoh | DOUT[31:0] hold
from MCLKf | Minimum |
| Tdout | MCLKf to D[31:0] valid | Maximum |
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