ARM7TDMI Technical Reference Manual 6.6. Multiply and multiply accumulate

6.6. Multiply and multiply accumulate

The multiply instructions use special hardware that implements integer multiplication with early termination. All cycles except the first are internal

The cycle timings are listed in the following tables:

multiply instruction cycle operations are listed in Table 6.5
multiply accumulate instruction cycle operations are listed in Table 6.6
multiply long instruction cycle operations are listed in Table 6.7
multiply accumulate long instruction cycle operations are listed in Table 6.8.

In Table 6.5 to Table 6.8:

m is the number of cycles required by the multiplication algorithm. See Instruction speed summary.

Table 6.5. Multiply instruction cycle operations

Cycle	Address	nRW	MAS[1:0]	Data	nMREQ	SEQ	nOPC
1	pc+2L	0	i	(pc+2L)	1	0	0
2	pc+3L	0	i	-	1	0	1
•	pc+3L	0	i	-	1	0	1
m	pc+3L	0	i	-	1	0	1
m+1	pc+3L	0	i	-	0	1	1
	pc+3L

Table 6.6. Multiply accumulate instruction cycle operations

Cycle	Address	nRW	MAS[1:0]	Data	nMREQ	SEQ	nOPC
1	pc+8	0	2	(pc+8)	1	0	0
2	pc+8	0	2	-	1	0	1
•	pc+12	0	2	-	1	0	1
m	pc+12	0	2	-	1	0	1
m+1	pc+12	0	2	-	1	0	1
m+2	pc+12	0	2	-	0	1	1
	pc+12

Table 6.7. Multiply long instruction cycle operations

Cycle	Address	nRW	MAS[1:0]	Data	nMREQ	SEQ	nOPC
1	pc+8	0	i	(pc+8)	1	0	0
2	pc+12	0	i	-	1	0	1
•	pc+12	0	i	-	1	0	1
m	pc+12	0	i	-	1	0	1
m+1	pc+12	0	i	-	1	0	1
m+2	pc+12	0	i	-	0	1	1
	pc+12

Table 6.8. Multiply accumulate long instruction cycle operations

Cycle	Address	nRW	MAS[1:0]	Data	nMREQ	SEQ	nOPC
1	pc+8	0	2	(pc+8)	1	0	0
2	pc+8	0	2	-	1	0	1
•	pc+12	0	2	-	1	0	1
m	pc+12	0	2	-	1	0	1
m+1	pc+12	0	2	-	1	0	1
m+2	pc+12	0	2	-	1	0	1
m+3	pc+12	0	2	-	0	1	1
	pc+12

Note

The multiply accumulate, multiply long, and multiply accumulate long operations are not available in Thumb state.

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