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A coprocessor data operation is a request from the core for the coprocessor to initiate some action. The action does not have to be completed for some time, but the coprocessor must commit to doing it before driving CPB LOW.
If the coprocessor is not capable of performing the requested task, it must leave CPA and CPB HIGH. If it can do the task, but cannot commit right now, it must drive CPA LOW but leave CPB HIGH until it can commit. The core busy-waits until CPB goes LOW.
The cycle timings are listed in Table 6.16 where:
b represents the busy cycles.
Table 6.16. Coprocessor data operation instruction cycle operations
CP status | Cycle | Address | nRW | MAS [1:0] | Data | nMREQ | SEQ | nOPC | nCPI | CPA | CPB |
|---|---|---|---|---|---|---|---|---|---|---|---|
ready | 1 | pc+8 | 0 | 2 | (pc+8) | 0 | 0 | 0 | 0 | 0 | 0 |
pc+12 | |||||||||||
not ready | 1 | pc+8 | 0 | 2 | (pc+8) | 1 | 0 | 0 | 0 | 0 | 1 |
2 | pc+8 | 0 | 2 | - | 1 | 0 | 1 | 0 | 0 | 1 | |
• | pc+8 | 0 | 2 | - | 1 | 0 | 1 | 0 | 0 | 1 | |
| b | pc+8 | 0 | 2 | - | 0 | 0 | 1 | 0 | 0 | 0 | |
pc+12 |
Coprocessor data operations are not available in Thumb state.
| Copyright © 1994-2001. All rights reserved. | ARM DDI 0029G |
| Non-Confidential | |
| PDF version | |
| Home > Instruction Cycle Timings > Coprocessor data operation |