6.10. Store multiple registers
The store multiple instruction proceeds very much as load
multiple instruction, without the final cycle. The abort handling
is much more straightforward as there is no wholesale overwriting
of registers.
The cycle timings are listed in Table 6.13 where:
Table 6.13. Store multiple registers instruction cycle operations
| Register | Cycle | Address | MAS[1:0] | nRW | Data | nMREQ | SEQ | nOPC |
|---|
Single register | 1 | pc+2L | i | 0 | (pc+2L) | 0 | 0 | 0 |
| 2 | alu | 2 | 1 | Ra | 0 | 0 | 1 |
| | pc+3L | | | | | | |
n registers (n>1) | 1 | pc+8 | i | 0 | (pc+2L) | 0 | 0 | 0 |
| | 2 | alu | 2 | 1 | Ra | 0 | 1 | 1 |
| | • | alu+• | 2 | 1 | R• | 0 | 1 | 1 |
| | n | alu+• | 2 | 1 | R• | 0 | 1 | 1 |
| | n+1 | alu+• | 2 | 1 | R• | 0 | 0 | 1 |
| | | pc+12 | | | | | | |
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