Due to the pipelined architecture of the CPU, instructions overlap considerably. In a typical cycle, one instruction can be using the data path while the next is being decoded and the one after that is being fetched. For this reason Table 6.23 presents the incremental number of cycles required by an instruction, rather than the total number of cycles for which the instruction uses part of the processor. Elapsed time, in cycles, for a routine can be calculated from these figures listed in Table 6.23. These figures assume that the instruction is actually executed. Unexecuted instructions take one cycle.

If the condition is not met then all instructions take one S-cycle. The cycle types N, S, I, and C are described in Bus cycle types .

In Table 6.23: