ARM7TDMI Technical Reference Manual 2.7. The program status registers

2.7. The program status registers

The ARM7TDMI processor contains a CPSR and five SPSRs for exception handlers to use. The program status registers:

hold information about the most recently performed ALU operation
control the enabling and disabling of interrupts
set the processor operating mode.

The arrangement of bits is shown in Figure 2.6.

Figure 2.6. Program status register format

Note

To maintain compatibility with future ARM processors, you must not alter any of the reserved bits. One method of preserving these bits is to use a read-write-modify strategy when changing the CPSR.

The remainder of this section describes:

Condition code flags
Control bits
Reserved bits .

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