In ARM state, 16 general registers and one or two status registers are accessible at any one time. In privileged modes, mode-specific banked registers become available. Figure 2-3 on page 2-10 shows which registers are available in each mode.

The ARM-state register set contains 16 directly-accessible registers, r0 to r15. A further register, the CPSR, contains condition code flags and the current mode bits. Registers r0 to r13 are general-purpose registers used to hold either data or address values. Registers r14 and r15 have the following special functions:

By convention, r13 is used as the Stack Pointer (SP).

In privileged modes, another register, the Saved Program Status Register (SPSR), is accessible. This contains the condition code flags and the mode bits saved as a result of the exception which caused entry to the current mode.

Banked registers are discrete physical registers in the core that are mapped to the available registers depending on the current processor operating mode. Banked register contents are preserved across operating mode changes.

FIQ mode has seven banked registers mapped to r8–r14 (r8_fiq–r14_fiq).

In ARM state, many FIQ handlers do not have to save any registers.

The User, IRQ, Supervisor, Abort, and undefined modes each have two banked registers mapped to r13 and r14, allowing a private SP and LR for each mode.

System mode shares the same registers as User mode.

Figure 2.3 shows the ARM-state registers.