ARM7TDMI Technical Reference Manual

(Rev 3)


Table of Contents

Preface
About this document
Intended audience
Using this manual
Typographical conventions
Timing diagram conventions
Further reading
ARM publications
Other publications
Feedback
Feedback on the ARM7TDMI core
Feedback on this document
1. Introduction
1.1. About the ARM7TDMI core
1.1.1. The instruction pipeline
1.1.2. Memory access
1.1.3. Memory interface
1.1.4. EmbeddedICE Logic
1.2. Architecture
1.2.1. Instruction compression
1.2.2. The Thumb instruction set
1.3. Block, core, and functional diagrams
1.4. Instruction set summary
1.4.1. Format summary
1.4.2. ARM instruction summary
1.4.3. Thumb instruction summary
2. Programmer’s Model
2.1. About the programmer’s model
2.2. Processor operating states
2.2.1. Switching state
2.3. Memory formats
2.3.1. Little-endian
2.3.2. Big-Endian
2.4. Data types
2.5. Operating modes
2.6. Registers
2.6.1. The ARM-state register set
2.6.2. The Thumb-state register set
2.6.3. The relationship between ARM-state and Thumb-state registers
2.6.4. Accessing high registers in Thumb state
2.7. The program status registers
2.7.1. Condition code flags
2.7.2. Control bits
2.7.3. Reserved bits
2.8. Exceptions
2.8.1. Exception entry and exit summary
2.8.2. Entering an exception
2.8.3. Leaving an exception
2.8.4. Fast interrupt request
2.8.5. Interrupt request
2.8.6. Abort
2.8.7. Software interrupt instruction
2.8.8. Undefined instruction
2.8.9. Exception vectors
2.8.10. Exception priorities
2.9. Interrupt latencies
2.9.1. Maximum interrupt latencies
2.9.2. Minimum interrupt latencies
2.10. Reset
3. Memory Interface
3.1. About the memory interface
3.2. Bus interface signals
3.3. Bus cycle types
3.3.1. Nonsequential cycles
3.3.2. Sequential cycles
3.3.3. Internal cycles
3.3.4. Merged IS cycles
3.3.5. Coprocessor register transfer cycles
3.3.6. Summary of ARM memory cycle timing
3.4. Addressing signals
3.4.1. A[31:0]
3.4.2. nRW
3.4.3. MAS[1:0]
3.4.4. nOPC
3.4.5. nTRANS
3.4.6. LOCK
3.4.7. TBIT
3.5. Address timing
3.6. Data timed signals
3.6.1. D[31:0], DOUT[31:0], and DIN[31:0]
3.6.2. ABORT
3.6.3. Byte latch enables
3.6.4. Byte and halfword accesses
3.7. Stretching access times
3.7.1. Modulating MCLK
3.7.2. Use of nWAIT to control bus cycles
3.8. Action of ARM7TDMI core in debug state
3.9. Privileged mode access
3.10. Reset sequence after power up
4. Coprocessor Interface
4.1. About coprocessors
4.1.1. Coprocessor availability
4.2. Coprocessor interface signals
4.3. Pipeline following signals
4.4. Coprocessor interface handshaking
4.4.1. The coprocessor
4.4.2. The ARM7TDMI processor
4.4.3. Coprocessor signaling
4.4.4. Consequences of busy-waiting
4.4.5. Coprocessor register transfer instructions
4.4.6. Coprocessor data operations
4.4.7. Coprocessor load and store operations
4.5. Connecting coprocessors
4.5.1. Connecting a single coprocessor
4.5.2. Connecting multiple coprocessors
4.6. If you are not using an external coprocessor
4.7. Undefined instructions
4.8. Privileged instructions
5. Debug Interface
5.1. About the debug interface
5.1.1. Stages of debug
5.1.2. Clocks
5.2. Debug systems
5.2.1. Debug host
5.2.2. Protocol converter
5.2.3. Debug target
5.3. Debug interface signals
5.3.1. Entry into debug state
5.3.2. Action of the processor in debug state
5.4. ARM7TDMI core clock domains
5.4.1. Clock switch during debug
5.4.2. Clock switch during test
5.5. Determining the core and system state
5.6. About EmbeddedICE Logic
5.7. Disabling EmbeddedICE
5.8. Debug Communications Channel
5.8.1. DCC registers
5.8.2. Communications through the DCC
6. Instruction Cycle Timings
6.1. About the instruction cycle timing tables
6.2. Branch and branch with link
6.3. Thumb branch with link
6.4. Branch and Exchange
6.5. Data operations
6.6. Multiply and multiply accumulate
6.7. Load register
6.8. Store register
6.9. Load multiple registers
6.10. Store multiple registers
6.11. Data swap
6.12. Software interrupt and exception entry
6.13. Coprocessor data operation
6.14. Coprocessor data transfer from memory to coprocessor
6.15. Coprocessor data transfer from coprocessor to memory
6.16. Coprocessor register transfer, load from coprocessor
6.17. Coprocessor register transfer, store to coprocessor
6.18. Undefined instructions and coprocessor absent
6.19. Unexecuted instructions
6.20. Instruction speed summary
7. AC and DC Parameters
7.1. Timing diagram information
7.2. General timing
7.3. Address bus enable control
7.4. Bidirectional data write cycle
7.5. Bidirectional data read cycle
7.6. Data bus control
7.7. Output 3-state timing
7.8. Unidirectional data write cycle timing
7.9. Unidirectional data read cycle timing
7.10. Configuration pin timing
7.11. Coprocessor timing
7.12. Exception timing
7.13. Synchronous interrupt timing
7.14. Debug timing
7.15. Debug communications channel output timing
7.16. Breakpoint timing
7.17. Test clock and external clock timing
7.18. Memory clock timing
7.19. Boundary scan general timing
7.20. Reset period timing
7.21. Output enable and disable times
7.22. Address latch enable control
7.23. Address pipeline control timing
7.24. Notes on AC Parameters
7.25. DC parameters
A. Signal Description
A.1. Signal description
A.1.1. Transistor dimensions
A.1.2. Signal types
A.1.3. Signals
B. Debug in Depth
B.1. Scan chains and JTAG interface
B.1.1. Scan chain implementation
B.1.2. TAP state machine
B.2. Resetting the TAP controller
B.3. Pullup resistors
B.4. Instruction register
B.5. Public instructions
B.5.1. EXTEST (0000)
B.5.2. SCAN_N (0010)
B.5.3. SAMPLE/PRELOAD (0011)
B.5.4. RESTART (0100)
B.5.5. CLAMP (0101)
B.5.6. HIGHZ (0111)
B.5.7. CLAMPZ (1001)
B.5.8. INTEST (1100)
B.5.9. IDCODE (1110)
B.5.10. BYPASS (1111)
B.6. Test data registers
B.6.1. Bypass register
B.6.2. ARM7TDMI core device IDentification (ID) code register
B.6.3. Instruction register
B.6.4. Scan path select register
B.6.5. Scan chains 0, 1, 2, and 3
B.7. The ARM7TDMI core clocks
B.7.1. Clock switch during debug
B.7.2. Clock switch during test
B.8. Determining the core and system state
B.8.1. Determining the core state
B.8.2. Determining system state
B.8.3. Exit from debug state
B.9. Behavior of the program counter during debug
B.9.1. Breakpoints
B.9.2. Watchpoints
B.9.3. Watchpoint with another exception
B.9.4. Debug request
B.9.5. System speed access
B.9.6. Summary of return address calculations
B.10. Priorities and exceptions
B.10.1. Breakpoint with Prefetch Abort
B.10.2. Interrupts
B.10.3. Data Aborts
B.11. Scan chain cell data
B.11.1. Scan chain 0 cells
B.11.2. Scan chain 1 cells
B.12. The watchpoint registers
B.12.1. Programming and reading watchpoint registers
B.12.2. Using the mask registers
B.12.3. The control registers
B.13. Programming breakpoints
B.13.1. Hardware breakpoints
B.13.2. Software breakpoints
B.14. Programming watchpoints
B.15. The debug control register
B.16. The debug status register
B.17. Coupling breakpoints and watchpoints
B.17.1. Breakpoint and watchpoint coupling example
B.17.2. RANGEOUT signal
B.18. EmbeddedICE timing
B.19. Programming Restriction
Glossary

List of Figures

1. Key to timing diagram conventions
1.1. Instruction pipeline
1.2. ARM7TDMI processor block diagram
1.3. Main processor
1.4. ARM7TDMI processor functional diagram
1.5. ARM instruction set formats
1.6. Thumb instruction set formats
2.1. LIttle-endian addresses of bytes and halfwords within words
2.2. Big-endian addresses of bytes and halfwords within words
2.3. Register organization in ARM state
2.4. Register organization in Thumb state
2.5. Mapping of Thumb-state registers onto ARM-state registers
2.6. Program status register format
3.1. Simple memory cycle
3.2. Nonsequential memory cycle
3.3. Sequential access cycles
3.4. Internal cycles
3.5. Merged IS cycle
3.6. Coprocessor register transfer cycles
3.7. Memory cycle timing
3.8. Pipelined addresses
3.9. Depipelined addresses
3.10. SRAM compatible address timing
3.11. External bus arrangement
3.12. Bidirectional bus timing
3.13. Unidirectional bus timing
3.14. External connection of unidirectional buses
3.15. Data write bus cycle
3.16. Data bus control circuit
3.17. Test chip data bus circuit
3.18. Memory access
3.19. Two cycle memory access
3.20. Data replication
3.21. Typical system timing
3.22. Reset sequence
4.1. Coprocessor busy-wait sequence
4.2. Coprocessor register transfer sequence
4.3. Coprocessor data operation sequence
4.4. Coprocessor load sequence
4.5. Coprocessor connections with bidirectional bus
4.6. Coprocessor connections with unidirectional bus
4.7. Connecting multiple coprocessors
5.1. Typical debug system
5.2. ARM7TDMI block diagram
5.3. Debug state entry
5.4. Clock switching on entry to debug state
5.5. ARM7TDM, TAP controller, and EmbeddedICE Logic
5.6. DCC control register format
7.1. General timing
7.2. ABE control timing
7.3. Bidirectional data write cycle timing
7.4. Bidirectional data read cycle timing
7.5. Data bus control timing
7.6. Output 3-state timing
7.7. Unidirectional data write cycle timing
7.8. Unidirectional data read cycle timing
7.9. Configuration pin timing
7.10. Coprocessor timing
7.11. Exception timing
7.12. Synchronous interrupt timing
7.13. Debug timing
7.14. DCC output timing
7.15. Breakpoint timing
7.16. TCK and ECLK timing
7.17. MCLK timing
7.18. Boundary scan general timing
7.19. Reset period timing
7.20. Output enable and disable times due to HIGHZ TAP instruction
7.21. Output enable and disable times due to data scanning
7.22. ALE control timing
7.23. APE control timing
B.1. ARM7TDMI core scan chain arrangements
B.2. Test access port controller state transitions
B.3. ID code register format
B.4. Input scan cell
B.5. Clock switching on entry to debug state
B.6. Debug exit sequence
B.7. EmbeddedICE block diagram
B.8. Watchpoint control value and mask format
B.9. Debug control register format
B.10. Debug status register format
B.11. Debug control and status register structure

List of Tables

1.1. Key to tables
1.2. ARM instruction summary
1.3. Addressing modes
1.4. Operand 2
1.5. Fields
1.6. Condition fields
1.7. Thumb instruction set summary
2.1. Register mode identifiers
2.2. PSR mode bit values
2.3. Exception entry and exit
2.4. Exception vectors
2.5. Exception priority order
3.1. Bus cycle types
3.2. Burst types
3.3. Significant address bits
3.4. nOPC
3.5. nTRANS encoding
3.6. Tristate control of processor outputs
3.7. Read accesses
3.8. Use of nM[4:0] to indicate current processor mode
4.1. Coprocessor availability
4.2. Handshaking signals
4.3. Summary of coprocessor signaling
4.4. Mode identifier signal meanings (nTRANS)
5.1. DCC register access instructions
6.1. Branch instruction cycle operations
6.2. Thumb long branch with link
6.3. Branch and exchange instruction cycle operations
6.4. Data operation instruction cycles
6.5. Multiply instruction cycle operations
6.6. Multiply accumulate instruction cycle operations
6.7. Multiply long instruction cycle operations
6.8. Multiply accumulate long instruction cycle operations
6.9. Load register instruction cycle operations
6.10. MAS[1:0] signal encoding
6.11. Store register instruction cycle operations
6.12. Load multiple registers instruction cycle operations
6.13. Store multiple registers instruction cycle operations
6.14. Data swap instruction cycle operations
6.15. Software Interrupt instruction cycle operations
6.16. Coprocessor data operation instruction cycle operations
6.17. Coprocessor data transfer instruction cycle operations
6.18. coprocessor data transfer instruction cycle operations
6.19. Coprocessor register transfer, load from coprocessor
6.20. Coprocessor register transfer, store to coprocessor
6.21. Undefined instruction cycle operations
6.22. Unexecuted instruction cycle operations
6.23. ARM instruction speed summary
7.1. General timing parameters
7.2. ABE control timing parameters
7.3. Bidirectional data write cycle timing parameters
7.4. Bidirectional data read cycle timing parameters
7.5. Data bus control timing parameters
7.6. Output 3-state time timing parameters
7.7. Unidirectional data write cycle timing parameters
7.8. Unidirectional data read cycle timing parameters
7.9. Configuration pin timing parameters
7.10. Coprocessor timing parameters
7.11. Exception timing parameters
7.12. Synchronous interrupt timing parameters
7.13. Debug timing parameters
7.14. DCC output timing parameters
7.15. Breakpoint timing parameters
7.16. TCK and ECLK timing parameters
7.17. MCLK timing parameters
7.18. Boundary scan general timing parameters
7.19. Reset period timing parameters
7.20. Output enable and disable timing parameters
7.21. ALE address control timing parameters
7.22. APE control timing parameters
7.23. AC timing parameters used in this chapter
A.1. Transistor sizes
A.2. Signal types
A.3. Signal Descriptions
B.1. Public instructions
B.2. Scan chain number allocation 
B.3. Scan chain 0 cells
B.4. Scan chain 1 cells
B.5. Function and mapping of EmbeddedICE registers 
B.6. MAS[1:0] signal encoding
B.7. Interrupt signal control

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The product described in this document is subject to continuous developments and improvements. All particulars of the product and its use contained in this document are given by ARM in good faith. However, all warranties implied or expressed, including but not limited to implied warranties of merchantability, or fitness for purpose, are excluded.

This document is intended only to assist the reader in the use of the product. ARM Limited shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product.

Figure B.2 reprinted with permission IEEE Std 1149.1-1990. IEEE Standard Test Access Port and Boundary Scan Architecture Copyright 1994-2001, by IEEE. The IEEE disclaims any responsibility or liability resulting from the placement and use in the described manner.

Confidentiality Status

This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this document to.

Product Status

The information in this document is final, that is for a developed product.

Revision History
Revision AOctober 1994Released.
Revision BDecember 1994First formal release.
Revision CDecember 1994Review comments added.
Revision DMarch 1995Technical changes.
Revision EAugust 1995Review comments added.
Revision FNovember 2000SGML, new layout, new title, incorporation of errata, and technical changes.
Revision GApril 2001Addition of timing parameters and editorial changes.
Copyright © 1994-2001. All rights reserved.ARM DDI 0029G
Non-Confidential