AMBA Test Interface Controller Data Sheet 1.3.2. Test Mode

1.3.2. Test Mode

In test mode the signal TestMode is driven HIGH. This forces BCLK to be driven from an external source (TCLK) and the External Bus Interface to provide a 32-bit bidirectional channel through which values can be read and written to BD. This 32-bit channel is referred to as TBUS, though in systems with a 32-bit external data bus TBUS will be identical to the external data bus. In AMBA systems which do not have a full 32-bit external data bus, address pins may have special test functionality (ie. connecting bidirectional PAD’s that can act as inputs during system test) to provide a TBUS connection.

The TREQA and TREQB signals should both be high on entering test mode. They are used to control the TIC which allows values to be read or written to any address location inside the microcontroller (it can not perform read or writes to external memory as the external bus is occupied by the test bus, TBUS). This is done by applying TIC vectors, of which there are three basic types; READ, WRITE and ADDRESS. Before a READ or WRITE vector can access a location the appropriate address must have been loaded. Thus at the beginning of testing the first vector should be an ADDRESS type.

Table 1.3. TIC vectors

TREQA	TREQB	Vector
1	1	ADDRESS. Must be first and last vector in a test sequence, also used as a turn around cycle after a write vector.
1	0	WRITE. Must be followed by a turn around cycle.
0	1	READ.
0	0	End of test. Must be proceeded by an ADDRESS vector.

Vectors are applied in a pipelined fashion. In Figure 1.2 vector 2 is applied while the AMBA transfer triggered by vector 1 is occurring. Then in the following cycle the transfer for vector 2 occurs (the diagram shows an extremely simplified case).

Figure 1.2. TIC vectors and AMBA transfers

When the vectors are applied the TACK signal should be monitored. This will normally be HIGH. However, if the transfer initiated by the previous vector is not complete, then TACK will go LOW off the falling edge of TCLK. When this occurs, the next vector should be held until TACK goes high. This is shown in Figure 1.3. Vector 1 starts a transfer with one wait cycle; vector 2 is held while the transfer completes.

Figure 1.3. Vectors and waited transfers

Although all vector types are applied as above, the timing characteristics for TBUS and the number of each vector type applied is vector dependant.

ADDRESS vector

Only one ADDRESS vector is required for an address transfer. The TBUS must be driven with the address value required during the ADDRESS vector transfer (ie. transfer 2 shown above). This value is latched from BD by the TIC, driven on to BA by the end of the ADDRESS vector transfer and is held for subsequent READ or WRITE vectors.

During an ADDRESS vector the TIC drives BTRAN as A-TRAN, thus no locations are accessed in the microcontroller.

WRITE vector

Only one WRITE vector is required for each write transfer. As with the ADDRESS vector; the value to be written should be driven on TBUS during the transfer for the WRITE vector. The TIC drives BTRAN as S-TRAN and asserts BWRITE, causing a write transfer to the address location setup by the last ADDRESS vector.

READ vector

Unlike ADDRESS or WRITE vectors the READ vector TBUS activity does not take place during its corresponding AMBA transfer. During the read transfer period the TBUS should be undriven. The value read by the READ vector is driven out on TBUS in the cycle following the transfer.

Figure 1.4. Read vectors and turn around

Here two reads are done (from the same address location). Since TBUS is driven in the cycle following the read 2 transfer; the READ vector 2 can not be followed by a WRITE or and ADDRESS vector (this would require TBUS to be driven by the tester in the cycle following the read 2 transfer). Thus a ‘turn around vector’ is needed. Turn around is indicated by TREQA=1, TREQB=1, which is identical to an ADDRESS vector. However, no address change occurs since TBUS is not driven and BD is not latched onto BA. The turn around vector may be followed by ADDRESS vectors (or any other type of vector) in which case the address will change in subsequent cycles.

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