| BCLK | In | - | System (bus) clock. This clock times all bus
transfers. The clock has two distinct phases. Phase 1 with BCLK LOW, and phase 2 with BCLK HIGH. |
| PA[8:0] | In | APB Bridge | This is the peripheral address bus, which is
used by an individualperipheral for decoding register accesses to
that peripheral.The addresses become valid before PSTB goes HIGH and remainvalid after PSTB goes LOW. |
| PD[5:0] | InOut | APB peripherals, BD bus | This is the bidirectional peripheral data bus.
The data bus is drivenby this block during read cycles (when PWRITE is LOW). |
| PSTB | In | APB Bridge | This strobe signal is used to time all accesses
on the peripheralbus. The falling edge of PSTB is
coincident with the falling edge of BCLK. |
| PWRITE | In | APB Bridge | When HIGH, this signal indicates a write to
a peripheral. WhenLOW, it indicates a read from a peripheral.This
signal has the same timing as the peripheral address bus. Itbecomes
valid before PSTB goes HIGH and
remains valid after goes LOW. |
| PSEL | In | APB Bridge | When HIGH, this signal indicates that this
module has beenselected by the APB bridge. This selection is a decode
of thesystem address bus (ASB). See AMBA Peripheral Bus Controller(ARM
DDI - 0044) for more details. |
| FIQESource | In | APB peripherals/external world | FIQ interrupt
signal into the Interrupt module. This active HIGHsignal indicates
that a Fast Interrupt Request has been generated. |
| IRQESource0 and IRQESource[5:2] | In | APB peripherals/external world | IRQ interrupt signals into the Interrupt module.
These active HIGHsignals indicate that interrupt requests have been
generated(IRQESource[1] is internally
generated in the Interrupt Controllermodule and is used to provide
a software triggered IRQ). |
| NFIQ | Out | ARM Core | Active LOW NFIQ interrupt
input to the ARM core. |
| NIRQ | Out | ARM Core | Active LOW NIRQ interrupt
input to the ARM core. |
| BnRES | In | Reset Controller | Reset signal generated from the Reset Controller. |
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