1.2. Hardware Interface and Signal Description

Table 1.1. APB signal descriptions

NameTypeSource/DestinationDescription

BCLK

In

System (bus) clock. This clock times all bus transfers. The clock has two distinct phases—phase 1 in which BCLK is LOW and phase 2 in which BCLK is HIGH.

PA[15:0]

In

APB Bridge

This is the peripheral address bus, which is used by individual peripherals for decoding register accesses to that peripheral.

The addresses become valid before PSTB goes HIGH and remains valid after PSTB goes LOW.

PD[15:0]

InOut

APB Peripherals, BD bus

This is the bidirectional peripheral data bus. The data bus is driven by this block during read cycles (when PWRITE is LOW).

PSTB

In

APB Bridge

This strobe signal is used to time all accesses on the peripheral bus. The falling edge of PSTB is coincident with the falling edge of BCLK.

PWRITE

In

APB Bridge

When HIGH, this signal indicates a write to a peripheral, and when LOW, a read from a peripheral.

This signal has the same timing as the peripheral address bus. It becomes valid before PSTB goes HIGH and remains valid after PSTB goes LOW.

PSEL

In

APB Bridge

When HIGH, this signal indicates the timer module has been selected by the APB bridge. This selection is a decode of the ASB system address bus. See AMBA Peripheral Bus Controller (ARM DDI 0044) for more details.

INTCT1

Out

APB peripherals

Active HIGH interrupt signal to the Interrupt Controller module. This signal indicates that an interrupt has been generated in timer 1.

INTCT2

Out

APB peripherals

Active HIGH interrupt signal to the Interrupt Controller module. This signal indicates that an interrupt has been generated in timer 2.

BnRES

In

Reset Controller

Active LOW bus reset signal.

Writes to the Timer module are generated from the Peripheral Bus Controller module. Figure 1.2 summarizes this.

Figure 1.2. Timer module APB write cycle

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