1.5. Timer Memory Map

The base address of the timers is not fixed and may be different for any particular system implementation. However, the offset of any particular register from the base address is fixed.

Table 1.2. Memory map of the timer APB peripheral

AddressRead LocationWrite Location
TimerBaseTimer1LoadTimer1Load
TimerBase + 0x04Timer1ValueReserved
TimerBase + 0x08Timer1ControlTimer1Control
TimerBase + 0x0C Timer1Clear
TimerBase + 0x20Timer2LoadTimer2Load
TimerBase + 0x24Timer2ValueReserved
TimerBase + 0x28Timer2ControlTimer2Control
TimerBase + 0x2C Timer2Clear
   
Test Registers
TimerBase + 0x10Timer1TestTimer1Test
TimerBase + 0x30Timer2TestTimer2Test
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